/*************************************************************************/ /*!
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@File
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@Title Device Memory Management
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description This file defines flags used on memory allocations and mappings
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These flags are relevant throughout the memory management
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software stack and are specified by users of services and
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understood by all levels of the memory management in both
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client and server.
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#ifndef PVRSRV_MEMALLOCFLAGS_H
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#define PVRSRV_MEMALLOCFLAGS_H
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#include "img_types.h"
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#if defined(SUPPORT_RGX)
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#include "rgx_memallocflags.h"
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#endif
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typedef IMG_UINT32 PVRSRV_MEMALLOCFLAGS_T;
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/*
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* --- MAPPING FLAGS ---
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* | 0-3 | 4-7 | 8-10 | 11-13 | 14 |
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* | GPU-RW | CPU-RW | GPU-Caching | CPU-Caching | KM-Mappable |
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*
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* --- MISC FLAGS ---
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* | 15 | 16 | 17 | 18 | 19 | 20 |
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* | Defer | CPU-Local | FW-Local | SVM | Sparse-Dummy-Page | CPU-Cache-Clean |
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*
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* --- DEV CONTROL FLAGS ---
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* | 24-27 |
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* | Device-Flags |
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*
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* --- MEMSET FLAGS ---
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* | 29 | 30 | 31 |
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* | Poison-On-Free | P.-On-Alloc | Zero-On-Alloc |
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*
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*/
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/*!
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* **********************************************************
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* * *
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* * MAPPING FLAGS *
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* * *
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* **********************************************************
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*/
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/*! PVRSRV_MEMALLOCFLAG_GPU_READABLE
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*
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* This flag affects the device MMU protection flags, and specifies
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* that the memory may be read by the GPU (is this always true?)
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*
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* Typically all device memory allocations would specify this flag.
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*
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* At the moment, memory allocations without this flag are not supported
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*
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* This flag will live with the PMR, thus subsequent mappings would
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* honour this flag.
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*
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* This is a dual purpose flag. It specifies that memory is permitted
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* to be read by the GPU, and also requests that the allocation is
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* mapped into the GPU as a readable mapping
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*
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* To be clear:
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* - When used as an argument on PMR creation; it specifies
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* that GPU readable mappings will be _permitted_
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* - When used as an argument to a "map" function: it specifies
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* that a GPU readable mapping is _desired_
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* - When used as an argument to "AllocDeviceMem": it specifies
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* that the PMR will be created with permission to be mapped
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* with a GPU readable mapping, _and_ that this PMR will be
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* mapped with a GPU readble mapping.
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* This distinction becomes important when (a) we export allocations;
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* and (b) when we separate the creation of the PMR from the mapping.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_READABLE (1U<<0)
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#define PVRSRV_CHECK_GPU_READABLE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_GPU_READABLE) != 0)
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/*! PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE
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*
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* This flag affects the device MMU protection flags, and specifies
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* that the memory may be written by the GPU
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*
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* Using this flag on an allocation signifies that the allocation is
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* intended to be written by the GPU.
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*
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* Omitting this flag causes a read-only mapping.
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*
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* This flag will live with the PMR, thus subsequent mappings would
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* honour this flag.
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*
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* This is a dual purpose flag. It specifies that memory is permitted
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* to be written by the GPU, and also requests that the allocation is
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* mapped into the GPU as a writable mapping (see note above about
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* permission vs. mapping mode, and why this flag causes permissions
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* to be inferred from mapping mode on first allocation)
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*
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* N.B. This flag has no relevance to the CPU's MMU mapping, if any,
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* and would therefore not enforce read-only mapping on CPU.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE (1U<<1) /*!< mapped as writable to the GPU */
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#define PVRSRV_CHECK_GPU_WRITEABLE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE) != 0)
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#define PVRSRV_MEMALLOCFLAG_GPU_READ_PERMITTED (1U<<2) /*!< can be mapped is GPU readable in another GPU mem context */
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#define PVRSRV_CHECK_GPU_READ_PERMITTED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_GPU_READ_PERMITTED) != 0)
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#define PVRSRV_MEMALLOCFLAG_GPU_WRITE_PERMITTED (1U<<3) /*!< can be mapped is GPU writable in another GPU mem context */
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#define PVRSRV_CHECK_GPU_WRITE_PERMITTED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_GPU_WRITE_PERMITTED) != 0)
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#define PVRSRV_MEMALLOCFLAG_CPU_READABLE (1U<<4) /*!< mapped as readable to the CPU */
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#define PVRSRV_CHECK_CPU_READABLE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_READABLE) != 0)
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#define PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE (1U<<5) /*!< mapped as writable to the CPU */
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#define PVRSRV_CHECK_CPU_WRITEABLE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE) != 0)
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#define PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED (1U<<6) /*!< can be mapped is CPU readable in another CPU mem context */
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#define PVRSRV_CHECK_CPU_READ_PERMITTED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED) != 0)
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#define PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED (1U<<7) /*!< can be mapped is CPU writable in another CPU mem context */
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#define PVRSRV_CHECK_CPU_WRITE_PERMITTED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED) != 0)
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/*
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* **********************************************************
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* * *
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* * CACHE CONTROL FLAGS *
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* * *
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* **********************************************************
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*/
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/*
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GPU domain
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==========
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The following defines are used to control the GPU cache bit field.
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The defines are mutually exclusive.
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A helper macro, PVRSRV_GPU_CACHE_MODE, is provided to obtain just the GPU cache
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bit field from the flags. This should be used whenever the GPU cache mode
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needs to be determined.
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*/
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/*! PVRSRV_MEMALLOCFLAG_GPU_UNCACHED
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GPU domain. Request uncached memory. This means that any writes to memory
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allocated with this flag are written straight to memory and thus are coherent
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for any device in the system.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_UNCACHED (0U<<8)
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#define PVRSRV_CHECK_GPU_UNCACHED(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_GPU_UNCACHED)
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/*! PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE
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GPU domain. Use write combiner (if supported) to combine sequential writes
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together to reduce memory access by doing burst writes.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE (1U<<8)
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#define PVRSRV_CHECK_GPU_WRITE_COMBINE(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE)
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/*! PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT
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GPU domain. This flag affects the GPU MMU protection flags.
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The allocation will be cached.
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Services will try to set the coherent bit in the GPU MMU tables so the
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GPU cache is snooping the CPU cache. If coherency is not supported the
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caller is responsible to ensure the caches are up to date.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT (2U<<8)
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#define PVRSRV_CHECK_GPU_CACHE_COHERENT(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT)
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/*! PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT
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GPU domain. Request cached memory, but not coherent (i.e. no cache snooping).
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This means that if the allocation needs to transition from one device
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to another services has to be informed so it can flush/invalidate the
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appropriate caches.
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Note: We reserve 3 bits in the CPU/GPU cache mode to allow for future
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expansion.
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT (3U<<8)
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#define PVRSRV_CHECK_GPU_CACHE_INCOHERENT(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT)
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/*! PVRSRV_MEMALLOCFLAG_GPU_CACHED
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GPU domain. This flag is for internal use only and is used to indicate
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that the underlying allocation should be cached on the GPU
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after all the snooping and coherent checks have been done
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_CACHED (7U<<8)
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#define PVRSRV_CHECK_GPU_CACHED(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_GPU_CACHED)
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/*! PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK
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GPU domain. GPU cache mode mask
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*/
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#define PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK (7U<<8)
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#define PVRSRV_GPU_CACHE_MODE(uiFlags) ((uiFlags) & PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK)
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/*
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CPU domain
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==========
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The following defines are used to control the CPU cache bit field.
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The defines are mutually exclusive.
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A helper macro, PVRSRV_CPU_CACHE_MODE, is provided to obtain just the CPU cache
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bit field from the flags. This should be used whenever the CPU cache mode
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needs to be determined.
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*/
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/*! PVRSRV_MEMALLOCFLAG_CPU_UNCACHED
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CPU domain. Request uncached memory. This means that any writes to memory
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allocated with this flag are written straight to memory and thus are coherent
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for any device in the system.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_UNCACHED (0U<<11)
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#define PVRSRV_CHECK_CPU_UNCACHED(uiFlags) (PVRSRV_CPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CPU_UNCACHED)
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/*! PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE
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CPU domain. Use write combiner (if supported) to combine sequential writes
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together to reduce memory access by doing burst writes.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE (1U<<11)
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#define PVRSRV_CHECK_CPU_WRITE_COMBINE(uiFlags) (PVRSRV_CPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE)
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/*! PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT
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CPU domain. This flag affects the CPU MMU protection flags.
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The allocation will be cached.
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Services will try to set the coherent bit in the CPU MMU tables so the
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CPU cache is snooping the GPU cache. If coherency is not supported the
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caller is responsible to ensure the caches are up to date.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT (2U<<11)
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#define PVRSRV_CHECK_CPU_CACHE_COHERENT(uiFlags) (PVRSRV_CPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT)
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/*! PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT
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CPU domain. Request cached memory, but not coherent (i.e. no cache snooping).
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This means that if the allocation needs to transition from one device
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to another services has to be informed so it can flush/invalidate the
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appropriate caches.
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Note: We reserve 3 bits in the CPU/GPU cache mode to allow for future
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expansion.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT (3U<<11)
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#define PVRSRV_CHECK_CPU_CACHE_INCOHERENT(uiFlags) (PVRSRV_CPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT)
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/*! PVRSRV_MEMALLOCFLAG_CPU_CACHED
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CPU domain. This flag is for internal use only and is used to indicate
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that the underlying allocation should be cached on the CPU
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after all the snooping and coherent checks have been done
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_CACHED (7U<<11)
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#define PVRSRV_CHECK_CPU_CACHED(uiFlags) (PVRSRV_CPU_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CPU_CACHED)
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/*!
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CPU domain. CPU cache mode mask
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK (7U<<11)
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#define PVRSRV_CPU_CACHE_MODE(uiFlags) ((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK)
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/* Helper flags for usual cases */
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/*! PVRSRV_MEMALLOCFLAG_UNCACHED
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* Memory will be uncached on CPU and GPU
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*/
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#define PVRSRV_MEMALLOCFLAG_UNCACHED (PVRSRV_MEMALLOCFLAG_GPU_UNCACHED | PVRSRV_MEMALLOCFLAG_CPU_UNCACHED)
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#define PVRSRV_CHECK_UNCACHED(uiFlags) (PVRSRV_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_UNCACHED)
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/*! PVRSRV_MEMALLOCFLAG_WRITE_COMBINE
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* Memory will be write-combined on CPU and GPU
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*/
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#define PVRSRV_MEMALLOCFLAG_WRITE_COMBINE (PVRSRV_MEMALLOCFLAG_GPU_WRITE_COMBINE | PVRSRV_MEMALLOCFLAG_CPU_WRITE_COMBINE)
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#define PVRSRV_CHECK_WRITE_COMBINE(uiFlags) (PVRSRV_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_WRITE_COMBINE)
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/*! PVRSRV_MEMALLOCFLAG_CACHE_COHERENT
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* Memory will be cached on CPU and GPU
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* Services will try to set the correct flags in the MMU tables.
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* In case there is no coherency support the caller has to ensure caches are up to date
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*/
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#define PVRSRV_MEMALLOCFLAG_CACHE_COHERENT (PVRSRV_MEMALLOCFLAG_GPU_CACHE_COHERENT | PVRSRV_MEMALLOCFLAG_CPU_CACHE_COHERENT)
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#define PVRSRV_CHECK_CACHE_COHERENT(uiFlags) (PVRSRV_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CACHE_COHERENT)
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/*! PVRSRV_MEMALLOCFLAG_CACHE_INCOHERENT
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* Memory will be cache-incoherent on CPU and GPU
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*/
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#define PVRSRV_MEMALLOCFLAG_CACHE_INCOHERENT (PVRSRV_MEMALLOCFLAG_GPU_CACHE_INCOHERENT | PVRSRV_MEMALLOCFLAG_CPU_CACHE_INCOHERENT)
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#define PVRSRV_CHECK_CACHE_INCOHERENT(uiFlags) (PVRSRV_CACHE_MODE(uiFlags) == PVRSRV_MEMALLOCFLAG_CACHE_INCOHERENT)
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/*!
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Cache mode mask
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*/
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#define PVRSRV_CACHE_MODE(uiFlags) (PVRSRV_GPU_CACHE_MODE(uiFlags) | PVRSRV_CPU_CACHE_MODE(uiFlags))
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/*!
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CPU MMU Flags mask -- intended for use internal to services only
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*/
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#define PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK (PVRSRV_MEMALLOCFLAG_CPU_READABLE | \
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PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE | \
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PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK)
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/*!
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MMU Flags mask -- intended for use internal to services only - used
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for partitioning the flags bits and determining which flags to pass
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down to mmu_common.c
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*/
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#define PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK (PVRSRV_MEMALLOCFLAG_GPU_READABLE | \
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PVRSRV_MEMALLOCFLAG_GPU_WRITEABLE | \
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PVRSRV_MEMALLOCFLAG_GPU_CACHE_MODE_MASK)
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/*!
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PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE
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Indicates that the PMR created due to this allocation will support
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in-kernel CPU mappings. Only privileged processes may use this
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flag as it may cause wastage of precious kernel virtual memory on
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some platforms.
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*/
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#define PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE (1U<<14)
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#define PVRSRV_CHECK_KERNEL_CPU_MAPPABLE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE) != 0)
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/*
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*
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* **********************************************************
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* * *
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* * ALLOC MEMORY FLAGS *
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* * *
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* **********************************************************
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*
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* (Bits 15)
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*
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*/
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#define PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC (1U<<15)
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#define PVRSRV_CHECK_ON_DEMAND(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC) != 0)
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/*!
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PVRSRV_MEMALLOCFLAG_CPU_LOCAL
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Indicates that the allocation will primarily be accessed by
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the CPU, so a UMA allocation (if available) is preferable.
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If not set, the allocation will primarily be accessed by
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the GPU, so LMA allocation (if available) is preferable.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_LOCAL (1U<<16)
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#define PVRSRV_CHECK_CPU_LOCAL(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_LOCAL) != 0)
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/*!
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PVRSRV_MEMALLOCFLAG_FW_LOCAL
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Indicates that the allocation will primarily be accessed by
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the FW.
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*/
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#define PVRSRV_MEMALLOCFLAG_FW_LOCAL (1U<<17)
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#define PVRSRV_CHECK_FW_LOCAL(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_FW_LOCAL) != 0)
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/*! PVRSRV_MEMALLOCFLAG_SVM
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Indicates that the allocation will be accessed by the
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CPU and GPU using the same virtual address, i.e. for
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all SVM allocs, IMG_CPU_VIRTADDR == IMG_DEV_VIRTADDR
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*/
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#define PVRSRV_MEMALLOCFLAG_SVM_ALLOC (1U<<18)
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#define PVRSRV_CHECK_SVM_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_SVM_ALLOC) != 0)
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/*! PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING
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Indicates the particular memory that's being allocated is sparse
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and the sparse regions should not be backed by dummy page */
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#define PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING (1U << 19)
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#define PVRSRV_IS_SPARSE_DUMMY_BACKING_REQUIRED(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING) == 0)
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/*! PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN
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Services is going to clean the cache for the allocated memory.
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For performance reasons avoid usage if allocation is written to by the CPU anyway
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before the next GPU kick.
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*/
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#define PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN (1U<<20)
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#define PVRSRV_CHECK_CPU_CACHE_CLEAN(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN) != 0)
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/*
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*
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* **********************************************************
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* * *
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* * MEMORY ZEROING AND POISONING FLAGS *
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* * *
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* **********************************************************
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*
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* Zero / Poison, on alloc/free
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*
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* We think the following usecases are required:
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*
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* don't poison or zero on alloc or free
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* (normal operation, also most efficient)
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* poison on alloc
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* (for helping to highlight bugs)
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* poison on alloc and free
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* (for helping to highlight bugs)
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* zero on alloc
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* (avoid highlighting security issues in other uses of memory)
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* zero on alloc and poison on free
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* (avoid highlighting security issues in other uses of memory,
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* while helping to highlight a subset of bugs e.g. memory
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* freed prematurely)
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*
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* Since there are more than 4, we can't encode this in just two bits,
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* so we might as well have a separate flag for each of the three
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* actions.
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*/
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/*! PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC
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Ensures that the memory allocated is initialised with zeroes.
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*/
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#define PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC (1U<<31)
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#define PVRSRV_CHECK_ZERO_ON_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC) != 0)
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#define PVRSRV_GET_ZERO_ON_ALLOC_FLAG(uiFlags) ((uiFlags) & PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC)
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/*! PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC
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Scribbles over the allocated memory with a poison value
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Not compatible with ZERO_ON_ALLOC
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Poisoning is very deliberately _not_ reflected in PDump as we want
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a simulation to cry loudly if the initialised data propagates to a
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result.
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*/
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#define PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC (1U<<30)
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#define PVRSRV_CHECK_POISON_ON_ALLOC(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC) != 0)
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/*! PVRSRV_MEMALLOCFLAG_POISON_ON_FREE
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Causes memory to be trashed when freed, as a lazy man's security
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measure.
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*/
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#define PVRSRV_MEMALLOCFLAG_POISON_ON_FREE (1U<<29)
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#define PVRSRV_CHECK_POISON_ON_FREE(uiFlags) (((uiFlags) & PVRSRV_MEMALLOCFLAG_POISON_ON_FREE) != 0)
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/*
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*
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* **********************************************************
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* * *
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* * Device specific MMU flags *
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* * *
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* **********************************************************
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*
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* (Bits 24 to 27)
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*
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* Some services controlled devices have device specific control
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* bits in their page table entries, we need to allow these flags
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* to be passed down the memory management layers so the user
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* can control these bits.
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*/
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#define PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_OFFSET 24
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#define PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK 0x0f000000UL
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#define PVRSRV_MEMALLOCFLAG_DEVICE_FLAG(n) \
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(((n) << PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_OFFSET) & \
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PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK)
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/*!
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* Secure buffer mask -- Flags in the mask are allowed for secure buffers
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* because they are not related to CPU mappings.
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*/
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#define PVRSRV_MEMALLOCFLAGS_SECBUFMASK ~(PVRSRV_MEMALLOCFLAG_CPU_CACHE_MODE_MASK | \
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PVRSRV_MEMALLOCFLAG_CPU_WRITEABLE | \
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PVRSRV_MEMALLOCFLAG_CPU_READABLE | \
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PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
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PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
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PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \
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PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \
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PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED)
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|
|
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/*!
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PMR flags mask -- for internal services use only. This is the set
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of flags that will be passed down and stored with the PMR, this also
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includes the MMU flags which the PMR has to pass down to mm_common.c
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at PMRMap time.
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*/
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#define PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \
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PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
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PVRSRV_MEMALLOCFLAG_KERNEL_CPU_MAPPABLE | \
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PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
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PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \
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PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
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PVRSRV_MEMALLOCFLAG_POISON_ON_FREE | \
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PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \
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PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING | \
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PVRSRV_MEMALLOCFLAG_FW_LOCAL | \
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PVRSRV_MEMALLOCFLAG_CPU_LOCAL)
|
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/*!
|
RA differentiation mask
|
|
for use internal to services
|
|
this is the set of flags bits that are able to determine whether a
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pair of allocations are permitted to live in the same page table.
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Allocations whose flags differ in any of these places would be
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allocated from separate RA Imports and therefore would never coexist
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in the same page.
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Special cases are zeroing and poisoning of memory. The caller is responsible
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to set the sub-allocations to the value he wants it to be. To differentiate
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between zeroed and poisoned RA Imports does not make sense because the
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memory might be reused.
|
|
*/
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#define PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK (PVRSRV_MEMALLOCFLAGS_PMRFLAGSMASK \
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& \
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~(PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
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PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC))
|
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/*!
|
Flags that affect _allocation_
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*/
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#define PVRSRV_MEMALLOCFLAGS_PERALLOCFLAGSMASK (0xFFFFFFFFU)
|
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/*!
|
Flags that affect _mapping_
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*/
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#define PVRSRV_MEMALLOCFLAGS_PERMAPPINGFLAGSMASK (PVRSRV_MEMALLOCFLAG_DEVICE_FLAGS_MASK | \
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PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAG_NO_OSPAGES_ON_ALLOC | \
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PVRSRV_MEMALLOCFLAG_SVM_ALLOC | \
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PVRSRV_MEMALLOCFLAG_SPARSE_NO_DUMMY_BACKING)
|
|
#if ((~(PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK) & PVRSRV_MEMALLOCFLAGS_PERMAPPINGFLAGSMASK) != 0)
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#error PVRSRV_MEMALLOCFLAGS_PERMAPPINGFLAGSMASK is not a subset of PVRSRV_MEMALLOCFLAGS_RA_DIFFERENTIATION_MASK
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#endif
|
|
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/*!
|
Flags that affect _physical allocations_ in the DevMemX API
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*/
|
#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_PHYSICAL_MASK (PVRSRV_MEMALLOCFLAGS_CPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAG_CPU_READ_PERMITTED | \
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PVRSRV_MEMALLOCFLAG_CPU_WRITE_PERMITTED | \
|
PVRSRV_MEMALLOCFLAG_CPU_CACHE_CLEAN | \
|
PVRSRV_MEMALLOCFLAG_CPU_LOCAL | \
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PVRSRV_MEMALLOCFLAG_ZERO_ON_ALLOC | \
|
PVRSRV_MEMALLOCFLAG_POISON_ON_ALLOC | \
|
PVRSRV_MEMALLOCFLAG_POISON_ON_FREE)
|
|
/*!
|
Flags that affect _virtual allocations_ in the DevMemX API
|
*/
|
#define PVRSRV_MEMALLOCFLAGS_DEVMEMX_VIRTUAL_MASK (PVRSRV_MEMALLOCFLAGS_GPU_MMUFLAGSMASK | \
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PVRSRV_MEMALLOCFLAG_GPU_READ_PERMITTED | \
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PVRSRV_MEMALLOCFLAG_GPU_WRITE_PERMITTED)
|
|
#endif /* #ifndef PVRSRV_MEMALLOCFLAGS_H */
|
