/*************************************************************************/ /*!
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@File physmem.c
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@Title Physmem
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Common entry point for creation of RAM backed PMR's
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /***************************************************************************/
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#include "img_types.h"
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#include "pvrsrv_error.h"
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#include "pvrsrv_memallocflags.h"
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#include "device.h"
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#include "physmem.h"
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#include "pvrsrv.h"
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#include "osfunc.h"
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#include "pdump_physmem.h"
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#include "pdump_km.h"
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#include "rgx_heaps.h"
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#if defined(DEBUG)
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IMG_UINT32 gPMRAllocFail = 0;
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#endif /* defined(DEBUG) */
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PVRSRV_ERROR DevPhysMemAlloc(PVRSRV_DEVICE_NODE *psDevNode,
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IMG_UINT32 ui32MemSize,
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const IMG_UINT8 u8Value,
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IMG_BOOL bInitPage,
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#if defined(PDUMP)
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const IMG_CHAR *pszDevSpace,
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const IMG_CHAR *pszSymbolicAddress,
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IMG_HANDLE *phHandlePtr,
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#endif
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IMG_HANDLE hMemHandle,
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IMG_DEV_PHYADDR *psDevPhysAddr)
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{
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void *pvCpuVAddr;
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PVRSRV_ERROR eError;
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#if defined(PDUMP)
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IMG_CHAR szFilenameOut[PDUMP_PARAM_MAX_FILE_NAME];
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PDUMP_FILEOFFSET_T uiOffsetOut;
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#endif
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PG_HANDLE *psMemHandle;
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IMG_UINT32 ui32PageSize;
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psMemHandle = hMemHandle;
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ui32PageSize = OSGetPageSize();
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/*Allocate the page */
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eError = psDevNode->pfnDevPxAlloc(psDevNode,
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TRUNCATE_64BITS_TO_SIZE_T(ui32MemSize),
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psMemHandle,
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psDevPhysAddr);
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if(PVRSRV_OK != eError)
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{
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PVR_DPF((PVR_DBG_ERROR,"Unable to allocate the pages"));
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return eError;
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}
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#if defined(PDUMP)
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eError = PDumpMalloc(pszDevSpace,
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pszSymbolicAddress,
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ui32MemSize,
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ui32PageSize,
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IMG_FALSE,
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0,
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IMG_FALSE,
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phHandlePtr);
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if(PVRSRV_OK != eError)
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{
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PDUMPCOMMENT("Allocating pages failed");
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*phHandlePtr = NULL;
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}
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#endif
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if(bInitPage)
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{
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/*Map the page to the CPU VA space */
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eError = psDevNode->pfnDevPxMap(psDevNode,
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psMemHandle,
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ui32MemSize,
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psDevPhysAddr,
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&pvCpuVAddr);
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if(PVRSRV_OK != eError)
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{
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PVR_DPF((PVR_DBG_ERROR,"Unable to map the allocated page"));
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psDevNode->pfnDevPxFree(psDevNode, psMemHandle);
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return eError;
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}
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/*Fill the memory with given content */
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/*NOTE: Wrong for the LMA + ARM64 combination, but this is unlikely */
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OSCachedMemSet(pvCpuVAddr, u8Value, ui32MemSize);
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/*Map the page to the CPU VA space */
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eError = psDevNode->pfnDevPxClean(psDevNode,
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psMemHandle,
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0,
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ui32MemSize);
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if(PVRSRV_OK != eError)
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{
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PVR_DPF((PVR_DBG_ERROR,"Unable to clean the allocated page"));
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psDevNode->pfnDevPxUnMap(psDevNode, psMemHandle, pvCpuVAddr);
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psDevNode->pfnDevPxFree(psDevNode, psMemHandle);
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return eError;
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}
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#if defined(PDUMP)
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/*P-Dumping of the page contents can be done in two ways
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* 1. Store the single byte init value to the .prm file
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* and load the same value to the entire dummy page buffer
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* This method requires lot of LDB's inserted into the out2.txt
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*
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* 2. Store the entire contents of the buffer to the .prm file
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* and load them back.
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* This only needs a single LDB instruction in the .prm file
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* and chosen this method
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* size of .prm file might go up but that's not huge at least
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* for this allocation
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*/
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/*Write the buffer contents to the prm file */
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eError = PDumpWriteBuffer(pvCpuVAddr,
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ui32MemSize,
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PDUMP_FLAGS_CONTINUOUS,
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szFilenameOut,
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sizeof(szFilenameOut),
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&uiOffsetOut);
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if(PVRSRV_OK == eError)
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{
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/* Load the buffer back to the allocated memory when playing the pdump */
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eError = PDumpPMRLDB(pszDevSpace,
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pszSymbolicAddress,
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0,
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ui32MemSize,
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szFilenameOut,
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uiOffsetOut,
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PDUMP_FLAGS_CONTINUOUS);
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if(PVRSRV_OK != eError)
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{
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PDUMP_ERROR(eError, "Failed to write LDB statement to script file");
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PVR_DPF((PVR_DBG_ERROR, "Failed to write LDB statement to script file, error %d", eError));
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}
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}
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else if (eError != PVRSRV_ERROR_PDUMP_NOT_ALLOWED)
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{
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PDUMP_ERROR(eError, "Failed to write device allocation to parameter file");
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PVR_DPF((PVR_DBG_ERROR, "Failed to write device allocation to parameter file, error %d", eError));
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}
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else
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{
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/* else Write to parameter file prevented under the flags and
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* current state of the driver so skip write to script and error IF.
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*/
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eError = PVRSRV_OK;
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}
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#endif
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/*UnMap the page */
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psDevNode->pfnDevPxUnMap(psDevNode,
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psMemHandle,
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pvCpuVAddr);
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}
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return PVRSRV_OK;
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}
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void DevPhysMemFree(PVRSRV_DEVICE_NODE *psDevNode,
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#if defined(PDUMP)
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IMG_HANDLE hPDUMPMemHandle,
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#endif
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IMG_HANDLE hMemHandle)
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{
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PG_HANDLE *psMemHandle;
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psMemHandle = hMemHandle;
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psDevNode->pfnDevPxFree(psDevNode, psMemHandle);
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#if defined(PDUMP)
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if(NULL != hPDUMPMemHandle)
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{
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PDumpFree(hPDUMPMemHandle);
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}
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#endif
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}
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PVRSRV_ERROR
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PhysmemNewRamBackedPMR(CONNECTION_DATA * psConnection,
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PVRSRV_DEVICE_NODE *psDevNode,
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IMG_DEVMEM_SIZE_T uiSize,
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PMR_SIZE_T uiChunkSize,
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IMG_UINT32 ui32NumPhysChunks,
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IMG_UINT32 ui32NumVirtChunks,
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IMG_UINT32 *pui32MappingTable,
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IMG_UINT32 uiLog2PageSize,
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PVRSRV_MEMALLOCFLAGS_T uiFlags,
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IMG_UINT32 uiAnnotationLength,
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const IMG_CHAR *pszAnnotation,
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PMR **ppsPMRPtr)
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{
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PVRSRV_DEVICE_PHYS_HEAP ePhysHeapIdx;
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PFN_SYS_DEV_CHECK_MEM_ALLOC_SIZE pfnCheckMemAllocSize =
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psDevNode->psDevConfig->pfnCheckMemAllocSize;
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PVR_UNREFERENCED_PARAMETER(psConnection);
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PVR_UNREFERENCED_PARAMETER(uiAnnotationLength);
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/* We don't currently support sparse memory with non OS page sized heaps */
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if (ui32NumVirtChunks > 1 && (uiLog2PageSize != OSGetPageShift()))
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{
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PVR_DPF((PVR_DBG_ERROR,
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"Requested page size for sparse 2^%u is not OS page size.",
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uiLog2PageSize));
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return PVRSRV_ERROR_INVALID_PARAMS;
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}
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/* Protect against ridiculous page sizes */
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if (uiLog2PageSize > RGX_HEAP_2MB_PAGE_SHIFT)
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{
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PVR_DPF((PVR_DBG_ERROR, "Page size is too big: 2^%u.", uiLog2PageSize));
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return PVRSRV_ERROR_INVALID_PARAMS;
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}
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/* Lookup the requested physheap index to use for this PMR allocation */
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if (PVRSRV_CHECK_FW_LOCAL(uiFlags))
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{
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ePhysHeapIdx = PVRSRV_DEVICE_PHYS_HEAP_FW_LOCAL;
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}
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else if (PVRSRV_CHECK_CPU_LOCAL(uiFlags))
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{
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ePhysHeapIdx = PVRSRV_DEVICE_PHYS_HEAP_CPU_LOCAL;
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}
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else
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{
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ePhysHeapIdx = PVRSRV_DEVICE_PHYS_HEAP_GPU_LOCAL;
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}
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/* Fail if requesting coherency on one side but uncached on the other */
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if ( (PVRSRV_CHECK_CPU_CACHE_COHERENT(uiFlags) &&
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(PVRSRV_CHECK_GPU_UNCACHED(uiFlags) || PVRSRV_CHECK_GPU_WRITE_COMBINE(uiFlags))) )
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{
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PVR_DPF((PVR_DBG_ERROR, "Request for CPU coherency but specifying GPU uncached "
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"Please use GPU cached flags for coherency."));
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return PVRSRV_ERROR_UNSUPPORTED_CACHE_MODE;
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}
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if ( (PVRSRV_CHECK_GPU_CACHE_COHERENT(uiFlags) &&
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(PVRSRV_CHECK_CPU_UNCACHED(uiFlags) || PVRSRV_CHECK_CPU_WRITE_COMBINE(uiFlags))) )
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{
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PVR_DPF((PVR_DBG_ERROR, "Request for GPU coherency but specifying CPU uncached "
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"Please use CPU cached flags for coherency."));
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return PVRSRV_ERROR_UNSUPPORTED_CACHE_MODE;
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}
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/* Apply memory budgeting policy */
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if (pfnCheckMemAllocSize)
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{
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IMG_UINT64 uiMemSize = (IMG_UINT64)uiChunkSize * ui32NumPhysChunks;
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PVRSRV_ERROR eError;
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eError = pfnCheckMemAllocSize(psDevNode->psDevConfig->hSysData, uiMemSize);
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if (eError != PVRSRV_OK)
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{
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return eError;
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}
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}
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#if defined(DEBUG)
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if (gPMRAllocFail > 0)
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{
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static IMG_UINT32 ui32AllocCount = 1;
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if (ui32AllocCount < gPMRAllocFail)
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{
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ui32AllocCount++;
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}
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else
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{
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PVR_DPF((PVR_DBG_ERROR, "%s failed on %d allocation.",
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__func__, ui32AllocCount));
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return PVRSRV_ERROR_OUT_OF_MEMORY;
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}
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}
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#endif /* defined(DEBUG) */
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return psDevNode->pfnCreateRamBackedPMR[ePhysHeapIdx](psDevNode,
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uiSize,
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uiChunkSize,
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ui32NumPhysChunks,
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ui32NumVirtChunks,
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pui32MappingTable,
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uiLog2PageSize,
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uiFlags,
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pszAnnotation,
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ppsPMRPtr);
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}
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PVRSRV_ERROR
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PhysmemNewRamBackedLockedPMR(CONNECTION_DATA * psConnection,
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PVRSRV_DEVICE_NODE *psDevNode,
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IMG_DEVMEM_SIZE_T uiSize,
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PMR_SIZE_T uiChunkSize,
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IMG_UINT32 ui32NumPhysChunks,
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IMG_UINT32 ui32NumVirtChunks,
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IMG_UINT32 *pui32MappingTable,
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IMG_UINT32 uiLog2PageSize,
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PVRSRV_MEMALLOCFLAGS_T uiFlags,
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IMG_UINT32 uiAnnotationLength,
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const IMG_CHAR *pszAnnotation,
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PMR **ppsPMRPtr)
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{
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PVRSRV_ERROR eError;
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eError = PhysmemNewRamBackedPMR(psConnection,
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psDevNode,
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uiSize,
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uiChunkSize,
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ui32NumPhysChunks,
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ui32NumVirtChunks,
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pui32MappingTable,
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uiLog2PageSize,
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uiFlags,
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uiAnnotationLength,
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pszAnnotation,
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ppsPMRPtr);
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if (eError == PVRSRV_OK)
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{
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eError = PMRLockSysPhysAddresses(*ppsPMRPtr);
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}
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return eError;
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}
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