/*************************************************************************/ /*!
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@File cache.h
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@Title CPU cache management header
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#ifndef _CACHE_KM_H_
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#define _CACHE_KM_H_
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#if defined(LINUX)
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#include <linux/version.h>
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#endif
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#include "pvrsrv_error.h"
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#include "img_types.h"
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#include "cache_ops.h"
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#include "device.h"
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#include "pmr.h"
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typedef IMG_UINT32 PVRSRV_CACHE_OP_ADDR_TYPE; /*!< Type represents address required for cache op. */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_VIRTUAL 0x1 /*!< Operation requires virtual address only */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_PHYSICAL 0x2 /*!< Operation requires physical address only */
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#define PVRSRV_CACHE_OP_ADDR_TYPE_BOTH 0x3 /*!< Operation requires both virtual & physical addresses */
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#define CACHEFLUSH_KM_RANGEBASED_DEFERRED 0x1 /*!< Services KM using deferred (i.e asynchronous) range-based flush */
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#define CACHEFLUSH_KM_RANGEBASED 0x2 /*!< Services KM using immediate (i.e synchronous) range-based flush */
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#define CACHEFLUSH_KM_GLOBAL 0x3 /*!< Services KM using global flush */
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#ifndef CACHEFLUSH_KM_TYPE /*!< Type represents cache maintenance operation method */
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#if defined(__x86__)
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/* Default for x86/x86_64 is global */
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#define CACHEFLUSH_KM_TYPE CACHEFLUSH_KM_GLOBAL
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#elif defined(__aarch64__)
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#if defined(LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0))
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/* Default here is range-based (i.e. no linux global flush) */
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#define CACHEFLUSH_KM_TYPE CACHEFLUSH_KM_RANGEBASED
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#else
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/* Default here is global (i.e. OS supports global flush) */
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#define CACHEFLUSH_KM_TYPE CACHEFLUSH_KM_GLOBAL
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#endif
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#else
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/* Default for other architecture is range-based */
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#define CACHEFLUSH_KM_TYPE CACHEFLUSH_KM_RANGEBASED
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#endif
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#else
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#if (CACHEFLUSH_KM_TYPE == CACHEFLUSH_KM_GLOBAL)
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#if defined(__mips__)
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/* Architecture does not support global cache maintenance */
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#error "CACHEFLUSH_KM_GLOBAL is not supported on architecture"
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#elif defined(__aarch64__)
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#if defined(LINUX) && (LINUX_VERSION_CODE >= KERNEL_VERSION(4,2,0))
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/* Linux revisions does not support global cache maintenance */
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#error "CACHEFLUSH_KM_GLOBAL is not supported on Linux v4.2 onwards"
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#endif
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#endif
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#endif
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#endif
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/*
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If we get multiple cache operations before the operation which will
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trigger the operation to happen then we need to make sure we do
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the right thing. Used for global cache maintenance
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*/
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#ifdef INLINE_IS_PRAGMA
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#pragma inline(SetCacheOp)
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#endif
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static INLINE PVRSRV_CACHE_OP SetCacheOp(PVRSRV_CACHE_OP uiCurrent, PVRSRV_CACHE_OP uiNew)
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{
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PVRSRV_CACHE_OP uiRet;
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uiRet = uiCurrent | uiNew;
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return uiRet;
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}
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/*
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Cache maintenance framework API
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*/
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PVRSRV_ERROR CacheOpInit(void);
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PVRSRV_ERROR CacheOpDeInit(void);
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/* This interface is always guaranteed to be synchronous */
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PVRSRV_ERROR CacheOpExec (PMR *psPMR,
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IMG_DEVMEM_OFFSET_T uiOffset,
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IMG_DEVMEM_SIZE_T uiSize,
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PVRSRV_CACHE_OP uiCacheOp);
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/* This interface _may_ defer cache-ops (i.e. asynchronous) */
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PVRSRV_ERROR CacheOpQueue (IMG_UINT32 ui32OpCount,
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PMR **ppsPMR,
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IMG_DEVMEM_OFFSET_T *puiOffset,
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IMG_DEVMEM_SIZE_T *puiSize,
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PVRSRV_CACHE_OP *puiCacheOp,
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IMG_UINT32 *pui32OpSeqNum);
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/* This interface is used to log user-mode cache-ops */
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PVRSRV_ERROR CacheOpLog (PMR *psPMR,
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IMG_DEVMEM_OFFSET_T uiOffset,
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IMG_DEVMEM_SIZE_T uiSize,
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IMG_UINT64 ui64QueuedTimeMs,
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IMG_UINT64 ui64ExecuteTimeMs,
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PVRSRV_CACHE_OP uiCacheOp);
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/* This interface must be used to fence for pending cache-ops before kicks */
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PVRSRV_ERROR CacheOpFence (RGXFWIF_DM eOpType, IMG_UINT32 ui32OpSeqNum);
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/* This interface is used for notification of completed cache-ops */
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PVRSRV_ERROR CacheOpSetTimeline (IMG_INT32 i32OpTimeline);
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/* This interface is used for retrieving the processor d-cache line size */
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PVRSRV_ERROR CacheOpGetLineSize (IMG_UINT32 *pui32L1DataCacheLineSize);
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#endif /* _CACHE_KM_H_ */
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