/*************************************************************************/ /*!
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@Title Test Chip Framework PDP register definitions
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@Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
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@Description Autogenerated C -- do not edit
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Generated from: tcf_rgbpdp_regs.def
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@License Dual MIT/GPLv2
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The contents of this file are subject to the MIT license as set out below.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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Alternatively, the contents of this file may be used under the terms of
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the GNU General Public License Version 2 ("GPL") in which case the provisions
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of GPL are applicable instead of those above.
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If you wish to allow use of your version of this file only under the terms of
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GPL, and not to allow others to use your version of this file under the terms
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of the MIT license, indicate your decision by deleting the provisions above
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and replace them with the notice and other provisions required by GPL as set
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out in the file called "GPL-COPYING" included in this distribution. If you do
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not delete the provisions above, a recipient may use your version of this file
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under the terms of either the MIT license or GPL.
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This License is also included in this distribution in the file called
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"MIT-COPYING".
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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
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BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
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COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/ /**************************************************************************/
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#if !defined(_TCF_RGBPDP_REGS_H_)
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#define _TCF_RGBPDP_REGS_H_
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/*
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Register PVR_TCF_RGBPDP_STR1SURF
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_STR1SURF 0x0000
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#define STR1HEIGHT_MASK 0x000007FFU
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#define STR1HEIGHT_SHIFT 0
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#define STR1HEIGHT_SIGNED 0
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#define STR1WIDTH_MASK 0x003FF800U
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#define STR1WIDTH_SHIFT 11
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#define STR1WIDTH_SIGNED 0
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#define STR1PIXFMT_MASK 0x0F000000U
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#define STR1PIXFMT_SHIFT 24
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#define STR1PIXFMT_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_STR1ADDRCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_STR1ADDRCTRL 0x0004
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#define STR1BASE_MASK 0x03FFFFFFU
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#define STR1BASE_SHIFT 0
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#define STR1BASE_SIGNED 0
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#define STR1INTFIELD_MASK 0x40000000U
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#define STR1INTFIELD_SHIFT 30
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#define STR1INTFIELD_SIGNED 0
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#define STR1STREN_MASK 0x80000000U
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#define STR1STREN_SHIFT 31
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#define STR1STREN_SIGNED 0
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/*
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Register PVR_PDP_STR1POSN
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*/
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#define TCF_RGBPDP_PVR_PDP_STR1POSN 0x0008
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#define STR1STRIDE_MASK 0x000003FFU
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#define STR1STRIDE_SHIFT 0
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#define STR1STRIDE_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_MEMCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_MEMCTRL 0x000C
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#define MEMREFRESH_MASK 0xC0000000U
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#define MEMREFRESH_SHIFT 30
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#define MEMREFRESH_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_STRCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_STRCTRL 0x0010
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#define BURSTLEN_GFX_MASK 0x000000FFU
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#define BURSTLEN_GFX_SHIFT 0
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#define BURSTLEN_GFX_SIGNED 0
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#define THRESHOLD_GFX_MASK 0x0000FF00U
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#define THRESHOLD_GFX_SHIFT 8
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#define THRESHOLD_GFX_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_SYNCCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_SYNCCTRL 0x0014
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#define HSDIS_MASK 0x00000001U
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#define HSDIS_SHIFT 0
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#define HSDIS_SIGNED 0
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#define HSPOL_MASK 0x00000002U
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#define HSPOL_SHIFT 1
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#define HSPOL_SIGNED 0
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#define VSDIS_MASK 0x00000004U
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#define VSDIS_SHIFT 2
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#define VSDIS_SIGNED 0
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#define VSPOL_MASK 0x00000008U
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#define VSPOL_SHIFT 3
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#define VSPOL_SIGNED 0
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#define BLNKDIS_MASK 0x00000010U
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#define BLNKDIS_SHIFT 4
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#define BLNKDIS_SIGNED 0
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#define BLNKPOL_MASK 0x00000020U
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#define BLNKPOL_SHIFT 5
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#define BLNKPOL_SIGNED 0
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#define HS_SLAVE_MASK 0x00000040U
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#define HS_SLAVE_SHIFT 6
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#define HS_SLAVE_SIGNED 0
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#define VS_SLAVE_MASK 0x00000080U
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#define VS_SLAVE_SHIFT 7
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#define VS_SLAVE_SIGNED 0
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#define INTERLACE_MASK 0x00000100U
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#define INTERLACE_SHIFT 8
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#define INTERLACE_SIGNED 0
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#define FIELDPOL_MASK 0x00000200U
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#define FIELDPOL_SHIFT 9
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#define FIELDPOL_SIGNED 0
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#define CLKPOL_MASK 0x00000800U
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#define CLKPOL_SHIFT 11
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#define CLKPOL_SIGNED 0
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#define CSYNC_EN_MASK 0x00001000U
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#define CSYNC_EN_SHIFT 12
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#define CSYNC_EN_SIGNED 0
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#define FIELD_EN_MASK 0x00002000U
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#define FIELD_EN_SHIFT 13
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#define FIELD_EN_SIGNED 0
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#define UPDWAIT_MASK 0x000F0000U
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#define UPDWAIT_SHIFT 16
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#define UPDWAIT_SIGNED 0
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#define UPDCTRL_MASK 0x01000000U
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#define UPDCTRL_SHIFT 24
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#define UPDCTRL_SIGNED 0
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#define UPDINTCTRL_MASK 0x02000000U
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#define UPDINTCTRL_SHIFT 25
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#define UPDINTCTRL_SIGNED 0
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#define UPDSYNCTRL_MASK 0x04000000U
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#define UPDSYNCTRL_SHIFT 26
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#define UPDSYNCTRL_SIGNED 0
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#define POWERDN_MASK 0x10000000U
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#define POWERDN_SHIFT 28
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#define POWERDN_SIGNED 0
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#define DISP_RST_MASK 0x20000000U
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#define DISP_RST_SHIFT 29
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#define DISP_RST_SIGNED 0
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#define SYNCACTIVE_MASK 0x80000000U
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#define SYNCACTIVE_SHIFT 31
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#define SYNCACTIVE_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_BORDCOL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_BORDCOL 0x0018
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#define BORDCOL_MASK 0x00FFFFFFU
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#define BORDCOL_SHIFT 0
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#define BORDCOL_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_UPDCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_UPDCTRL 0x001C
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#define UPDFIELD_MASK 0x00000001U
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#define UPDFIELD_SHIFT 0
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#define UPDFIELD_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_HSYNC1
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC1 0x0020
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#define HT_MASK 0x00000FFFU
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#define HT_SHIFT 0
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#define HT_SIGNED 0
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#define HBPS_MASK 0x0FFF0000U
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#define HBPS_SHIFT 16
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#define HBPS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_HSYNC2
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC2 0x0024
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#define HLBS_MASK 0x00000FFFU
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#define HLBS_SHIFT 0
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#define HLBS_SIGNED 0
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#define HAS_MASK 0x0FFF0000U
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#define HAS_SHIFT 16
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#define HAS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_HSYNC3
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_HSYNC3 0x0028
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#define HRBS_MASK 0x00000FFFU
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#define HRBS_SHIFT 0
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#define HRBS_SIGNED 0
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#define HFPS_MASK 0x0FFF0000U
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#define HFPS_SHIFT 16
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#define HFPS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_VSYNC1
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC1 0x002C
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#define VT_MASK 0x00000FFFU
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#define VT_SHIFT 0
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#define VT_SIGNED 0
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#define VBPS_MASK 0x0FFF0000U
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#define VBPS_SHIFT 16
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#define VBPS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_VSYNC2
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC2 0x0030
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#define VTBS_MASK 0x00000FFFU
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#define VTBS_SHIFT 0
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#define VTBS_SIGNED 0
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#define VAS_MASK 0x0FFF0000U
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#define VAS_SHIFT 16
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#define VAS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_VSYNC3
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_VSYNC3 0x0034
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#define VBBS_MASK 0x00000FFFU
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#define VBBS_SHIFT 0
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#define VBBS_SIGNED 0
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#define VFPS_MASK 0x0FFF0000U
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#define VFPS_SHIFT 16
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#define VFPS_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_HDECTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_HDECTRL 0x0038
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#define HDEF_MASK 0x00000FFFU
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#define HDEF_SHIFT 0
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#define HDEF_SIGNED 0
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#define HDES_MASK 0x0FFF0000U
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#define HDES_SHIFT 16
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#define HDES_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_VDECTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_VDECTRL 0x003C
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#define VDEF_MASK 0x00000FFFU
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#define VDEF_SHIFT 0
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#define VDEF_SIGNED 0
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#define VDES_MASK 0x0FFF0000U
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#define VDES_SHIFT 16
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#define VDES_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_VEVENT
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_VEVENT 0x0040
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#define VFETCH_MASK 0x00000FFFU
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#define VFETCH_SHIFT 0
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#define VFETCH_SIGNED 0
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#define VEVENT_MASK 0x0FFF0000U
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#define VEVENT_SHIFT 16
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#define VEVENT_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_OPMASK
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_OPMASK 0x0044
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#define MASKR_MASK 0x000000FFU
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#define MASKR_SHIFT 0
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#define MASKR_SIGNED 0
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#define MASKG_MASK 0x0000FF00U
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#define MASKG_SHIFT 8
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#define MASKG_SIGNED 0
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#define MASKB_MASK 0x00FF0000U
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#define MASKB_SHIFT 16
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#define MASKB_SIGNED 0
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#define BLANKLEVEL_MASK 0x40000000U
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#define BLANKLEVEL_SHIFT 30
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#define BLANKLEVEL_SIGNED 0
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#define MASKLEVEL_MASK 0x80000000U
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#define MASKLEVEL_SHIFT 31
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#define MASKLEVEL_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_INTSTAT
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTSTAT 0x0048
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#define INTS_HBLNK0_MASK 0x00000001U
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#define INTS_HBLNK0_SHIFT 0
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#define INTS_HBLNK0_SIGNED 0
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#define INTS_HBLNK1_MASK 0x00000002U
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#define INTS_HBLNK1_SHIFT 1
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#define INTS_HBLNK1_SIGNED 0
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#define INTS_VBLNK0_MASK 0x00000004U
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#define INTS_VBLNK0_SHIFT 2
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#define INTS_VBLNK0_SIGNED 0
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#define INTS_VBLNK1_MASK 0x00000008U
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#define INTS_VBLNK1_SHIFT 3
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#define INTS_VBLNK1_SIGNED 0
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#define INTS_STR1URUN_MASK 0x00000010U
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#define INTS_STR1URUN_SHIFT 4
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#define INTS_STR1URUN_SIGNED 0
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#define INTS_STR1ORUN_MASK 0x00000020U
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#define INTS_STR1ORUN_SHIFT 5
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#define INTS_STR1ORUN_SIGNED 0
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#define INTS_DISPURUN_MASK 0x00000040U
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#define INTS_DISPURUN_SHIFT 6
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#define INTS_DISPURUN_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_INTENAB
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTENAB 0x004C
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#define INTEN_HBLNK0_MASK 0x00000001U
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#define INTEN_HBLNK0_SHIFT 0
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#define INTEN_HBLNK0_SIGNED 0
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#define INTEN_HBLNK1_MASK 0x00000002U
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#define INTEN_HBLNK1_SHIFT 1
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#define INTEN_HBLNK1_SIGNED 0
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#define INTEN_VBLNK0_MASK 0x00000004U
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#define INTEN_VBLNK0_SHIFT 2
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#define INTEN_VBLNK0_SIGNED 0
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#define INTEN_VBLNK1_MASK 0x00000008U
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#define INTEN_VBLNK1_SHIFT 3
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#define INTEN_VBLNK1_SIGNED 0
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#define INTEN_STR1URUN_MASK 0x00000010U
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#define INTEN_STR1URUN_SHIFT 4
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#define INTEN_STR1URUN_SIGNED 0
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#define INTEN_STR1ORUN_MASK 0x00000020U
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#define INTEN_STR1ORUN_SHIFT 5
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#define INTEN_STR1ORUN_SIGNED 0
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#define INTEN_DISPURUN_MASK 0x00000040U
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#define INTEN_DISPURUN_SHIFT 6
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#define INTEN_DISPURUN_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_INTCLEAR
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTCLEAR 0x0050
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#define INTCLR_HBLNK0_MASK 0x00000001U
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#define INTCLR_HBLNK0_SHIFT 0
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#define INTCLR_HBLNK0_SIGNED 0
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#define INTCLR_HBLNK1_MASK 0x00000002U
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#define INTCLR_HBLNK1_SHIFT 1
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#define INTCLR_HBLNK1_SIGNED 0
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#define INTCLR_VBLNK0_MASK 0x00000004U
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#define INTCLR_VBLNK0_SHIFT 2
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#define INTCLR_VBLNK0_SIGNED 0
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#define INTCLR_VBLNK1_MASK 0x00000008U
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#define INTCLR_VBLNK1_SHIFT 3
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#define INTCLR_VBLNK1_SIGNED 0
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#define INTCLR_STR1URUN_MASK 0x00000010U
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#define INTCLR_STR1URUN_SHIFT 4
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#define INTCLR_STR1URUN_SIGNED 0
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#define INTCLR_STR1ORUN_MASK 0x00000020U
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#define INTCLR_STR1ORUN_SHIFT 5
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#define INTCLR_STR1ORUN_SIGNED 0
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#define INTCLR_DISPURUN_MASK 0x00000040U
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#define INTCLR_DISPURUN_SHIFT 6
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#define INTCLR_DISPURUN_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_INTCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_INTCTRL 0x0054
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#define HBLNK_LINENO_MASK 0x00000FFFU
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#define HBLNK_LINENO_SHIFT 0
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#define HBLNK_LINENO_SIGNED 0
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#define HBLNK_LINE_MASK 0x00010000U
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#define HBLNK_LINE_SHIFT 16
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#define HBLNK_LINE_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_SIGNAT
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_SIGNAT 0x0058
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#define SIGNATURE_MASK 0xFFFFFFFFU
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#define SIGNATURE_SHIFT 0
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#define SIGNATURE_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_LINESTAT
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_LINESTAT 0x005C
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#define LINENO_MASK 0x00000FFFU
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#define LINENO_SHIFT 0
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#define LINENO_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_DBGCTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGCTRL 0x0060
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#define DBG_ENAB_MASK 0x00000001U
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#define DBG_ENAB_SHIFT 0
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#define DBG_ENAB_SIGNED 0
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#define DBG_READ_MASK 0x00000002U
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#define DBG_READ_SHIFT 1
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#define DBG_READ_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_DBGDATA
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGDATA 0x0064
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#define DBG_DATA_MASK 0x00FFFFFFU
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#define DBG_DATA_SHIFT 0
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#define DBG_DATA_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_DBGSIDE
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_DBGSIDE 0x0068
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#define DBG_SIDE_MASK 0x00000007U
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#define DBG_SIDE_SHIFT 0
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#define DBG_SIDE_SIGNED 0
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#define DBG_VAL_MASK 0x00000008U
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#define DBG_VAL_SHIFT 3
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#define DBG_VAL_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_REGLD_STAT
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_REGLD_STAT 0x0070
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#define REGLD_ADDROUT_MASK 0x00FFFFFFU
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#define REGLD_ADDROUT_SHIFT 0
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#define REGLD_ADDROUT_SIGNED 0
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#define REGLD_ADDREN_MASK 0x80000000U
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#define REGLD_ADDREN_SHIFT 31
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#define REGLD_ADDREN_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_REGLD_CTRL
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_REGLD_CTRL 0x0074
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#define REGLD_ADDRIN_MASK 0x00FFFFFFU
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#define REGLD_ADDRIN_SHIFT 0
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#define REGLD_ADDRIN_SIGNED 0
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#define REGLD_VAL_MASK 0x01000000U
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#define REGLD_VAL_SHIFT 24
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#define REGLD_VAL_SIGNED 0
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#define REGLD_ADDRLEN_MASK 0xFE000000U
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#define REGLD_ADDRLEN_SHIFT 25
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#define REGLD_ADDRLEN_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_CORE_ID
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_CORE_ID 0x0078
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#define CONFIG_ID_MASK 0x0000FFFFU
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#define CONFIG_ID_SHIFT 0
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#define CONFIG_ID_SIGNED 0
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#define CORE_ID_MASK 0x00FF0000U
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#define CORE_ID_SHIFT 16
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#define CORE_ID_SIGNED 0
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#define GROUP_ID_MASK 0xFF000000U
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#define GROUP_ID_SHIFT 24
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#define GROUP_ID_SIGNED 0
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/*
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Register PVR_TCF_RGBPDP_CORE_REV
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*/
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#define TCF_RGBPDP_PVR_TCF_RGBPDP_CORE_REV 0x007C
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#define MAINT_REV_MASK 0x000000FFU
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#define MAINT_REV_SHIFT 0
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#define MAINT_REV_SIGNED 0
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#define MINOR_REV_MASK 0x0000FF00U
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#define MINOR_REV_SHIFT 8
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#define MINOR_REV_SIGNED 0
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#define MAJOR_REV_MASK 0x00FF0000U
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#define MAJOR_REV_SHIFT 16
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#define MAJOR_REV_SIGNED 0
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#endif /* !defined(_TCF_RGBPDP_REGS_H_) */
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/*****************************************************************************
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End of file (tcf_rgbpdp_regs.h)
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*****************************************************************************/
|
