/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2017-2018 Intel Corporation
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*/
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#ifndef __I915_PMU_H__
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#define __I915_PMU_H__
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#include <linux/hrtimer.h>
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#include <linux/perf_event.h>
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#include <linux/spinlock_types.h>
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#include <drm/i915_drm.h>
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struct drm_i915_private;
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enum {
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__I915_SAMPLE_FREQ_ACT = 0,
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__I915_SAMPLE_FREQ_REQ,
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__I915_SAMPLE_RC6,
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__I915_SAMPLE_RC6_ESTIMATED,
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__I915_NUM_PMU_SAMPLERS
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};
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/**
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* How many different events we track in the global PMU mask.
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*
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* It is also used to know to needed number of event reference counters.
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*/
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#define I915_PMU_MASK_BITS \
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((1 << I915_PMU_SAMPLE_BITS) + \
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(I915_PMU_LAST + 1 - __I915_PMU_OTHER(0)))
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struct i915_pmu_sample {
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u64 cur;
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};
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struct i915_pmu {
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/**
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* @node: List node for CPU hotplug handling.
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*/
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struct hlist_node node;
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/**
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* @base: PMU base.
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*/
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struct pmu base;
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/**
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* @lock: Lock protecting enable mask and ref count handling.
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*/
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spinlock_t lock;
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/**
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* @timer: Timer for internal i915 PMU sampling.
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*/
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struct hrtimer timer;
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/**
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* @enable: Bitmask of all currently enabled events.
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*
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* Bits are derived from uAPI event numbers in a way that low 16 bits
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* correspond to engine event _sample_ _type_ (I915_SAMPLE_QUEUED is
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* bit 0), and higher bits correspond to other events (for instance
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* I915_PMU_ACTUAL_FREQUENCY is bit 16 etc).
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*
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* In other words, low 16 bits are not per engine but per engine
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* sampler type, while the upper bits are directly mapped to other
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* event types.
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*/
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u64 enable;
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/**
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* @timer_last:
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*
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* Timestmap of the previous timer invocation.
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*/
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ktime_t timer_last;
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/**
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* @enable_count: Reference counts for the enabled events.
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*
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* Array indices are mapped in the same way as bits in the @enable field
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* and they are used to control sampling on/off when multiple clients
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* are using the PMU API.
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*/
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unsigned int enable_count[I915_PMU_MASK_BITS];
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/**
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* @timer_enabled: Should the internal sampling timer be running.
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*/
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bool timer_enabled;
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/**
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* @sample: Current and previous (raw) counters for sampling events.
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*
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* These counters are updated from the i915 PMU sampling timer.
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*
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* Only global counters are held here, while the per-engine ones are in
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* struct intel_engine_cs.
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*/
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struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
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/**
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* @suspended_jiffies_last: Cached suspend time from PM core.
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*/
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unsigned long suspended_jiffies_last;
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/**
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* @i915_attr: Memory block holding device attributes.
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*/
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void *i915_attr;
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/**
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* @pmu_attr: Memory block holding device attributes.
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*/
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void *pmu_attr;
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};
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#ifdef CONFIG_PERF_EVENTS
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void i915_pmu_register(struct drm_i915_private *i915);
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void i915_pmu_unregister(struct drm_i915_private *i915);
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void i915_pmu_gt_parked(struct drm_i915_private *i915);
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void i915_pmu_gt_unparked(struct drm_i915_private *i915);
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#else
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static inline void i915_pmu_register(struct drm_i915_private *i915) {}
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static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
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static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
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static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
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#endif
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#endif
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