// SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note
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/*
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*
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* (C) COPYRIGHT 2014-2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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/*
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* GPU backend instrumentation APIs.
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*/
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#include <mali_kbase.h>
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#include <gpu/mali_kbase_gpu_regmap.h>
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#include <mali_kbase_hwaccess_instr.h>
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#include <device/mali_kbase_device.h>
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#include <backend/gpu/mali_kbase_instr_internal.h>
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int kbase_instr_hwcnt_enable_internal(struct kbase_device *kbdev,
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struct kbase_context *kctx,
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struct kbase_instr_hwcnt_enable *enable)
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{
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unsigned long flags;
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int err = -EINVAL;
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u32 irq_mask;
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u32 prfcnt_config;
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lockdep_assert_held(&kbdev->hwaccess_lock);
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/* alignment failure */
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if ((enable->dump_buffer == 0ULL) || (enable->dump_buffer & (2048 - 1)))
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goto out_err;
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.backend.state != KBASE_INSTR_STATE_DISABLED) {
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/* Instrumentation is already enabled */
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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goto out_err;
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}
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/* Enable interrupt */
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irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK));
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK), irq_mask |
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PRFCNT_SAMPLE_COMPLETED);
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/* In use, this context is the owner */
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kbdev->hwcnt.kctx = kctx;
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/* Remember the dump address so we can reprogram it later */
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kbdev->hwcnt.addr = enable->dump_buffer;
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kbdev->hwcnt.addr_bytes = enable->dump_buffer_bytes;
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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/* Configure */
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prfcnt_config = kctx->as_nr << PRFCNT_CONFIG_AS_SHIFT;
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#ifdef CONFIG_MALI_PRFCNT_SET_SELECT_VIA_DEBUG_FS
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prfcnt_config |= kbdev->hwcnt.backend.override_counter_set
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<< PRFCNT_CONFIG_SETSELECT_SHIFT;
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#else
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prfcnt_config |= enable->counter_set << PRFCNT_CONFIG_SETSELECT_SHIFT;
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#endif
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG),
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prfcnt_config | PRFCNT_CONFIG_MODE_OFF);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO),
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enable->dump_buffer & 0xFFFFFFFF);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI),
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enable->dump_buffer >> 32);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_JM_EN),
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enable->fe_bm);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_SHADER_EN),
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enable->shader_bm);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_MMU_L2_EN),
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enable->mmu_l2_bm);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_TILER_EN),
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enable->tiler_bm);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG),
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prfcnt_config | PRFCNT_CONFIG_MODE_MANUAL);
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_IDLE;
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kbdev->hwcnt.backend.triggered = 1;
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wake_up(&kbdev->hwcnt.backend.wait);
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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err = 0;
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dev_dbg(kbdev->dev, "HW counters dumping set-up for context %pK", kctx);
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return err;
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out_err:
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return err;
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}
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int kbase_instr_hwcnt_disable_internal(struct kbase_context *kctx)
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{
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unsigned long flags, pm_flags;
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int err = -EINVAL;
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u32 irq_mask;
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struct kbase_device *kbdev = kctx->kbdev;
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while (1) {
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spin_lock_irqsave(&kbdev->hwaccess_lock, pm_flags);
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_DISABLED) {
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/* Instrumentation is not enabled */
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, pm_flags);
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goto out;
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}
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if (kbdev->hwcnt.kctx != kctx) {
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/* Instrumentation has been setup for another context */
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, pm_flags);
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goto out;
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}
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if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_IDLE)
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break;
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, pm_flags);
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/* Ongoing dump/setup - wait for its completion */
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wait_event(kbdev->hwcnt.backend.wait,
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kbdev->hwcnt.backend.triggered != 0);
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}
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_DISABLED;
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kbdev->hwcnt.backend.triggered = 0;
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/* Disable interrupt */
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irq_mask = kbase_reg_read(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK));
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_IRQ_MASK),
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irq_mask & ~PRFCNT_SAMPLE_COMPLETED);
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/* Disable the counters */
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_CONFIG), 0);
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kbdev->hwcnt.kctx = NULL;
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kbdev->hwcnt.addr = 0ULL;
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kbdev->hwcnt.addr_bytes = 0ULL;
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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spin_unlock_irqrestore(&kbdev->hwaccess_lock, pm_flags);
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dev_dbg(kbdev->dev, "HW counters dumping disabled for context %pK",
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kctx);
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err = 0;
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out:
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return err;
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}
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int kbase_instr_hwcnt_request_dump(struct kbase_context *kctx)
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{
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unsigned long flags;
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int err = -EINVAL;
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struct kbase_device *kbdev = kctx->kbdev;
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.kctx != kctx) {
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/* The instrumentation has been setup for another context */
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goto unlock;
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}
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if (kbdev->hwcnt.backend.state != KBASE_INSTR_STATE_IDLE) {
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/* HW counters are disabled or another dump is ongoing, or we're
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* resetting
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*/
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goto unlock;
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}
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kbdev->hwcnt.backend.triggered = 0;
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/* Mark that we're dumping - the PF handler can signal that we faulted
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*/
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_DUMPING;
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/* Reconfigure the dump address */
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_LO),
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kbdev->hwcnt.addr & 0xFFFFFFFF);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(PRFCNT_BASE_HI),
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kbdev->hwcnt.addr >> 32);
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/* Start dumping */
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_PRFCNT_SAMPLE, NULL,
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kbdev->hwcnt.addr);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND),
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GPU_COMMAND_PRFCNT_SAMPLE);
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dev_dbg(kbdev->dev, "HW counters dumping done for context %pK", kctx);
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err = 0;
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unlock:
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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return err;
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}
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KBASE_EXPORT_SYMBOL(kbase_instr_hwcnt_request_dump);
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bool kbase_instr_hwcnt_dump_complete(struct kbase_context *kctx,
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bool * const success)
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{
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unsigned long flags;
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bool complete = false;
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struct kbase_device *kbdev = kctx->kbdev;
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_IDLE) {
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*success = true;
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complete = true;
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} else if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_FAULT) {
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*success = false;
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complete = true;
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_IDLE;
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}
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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return complete;
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}
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KBASE_EXPORT_SYMBOL(kbase_instr_hwcnt_dump_complete);
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void kbase_instr_hwcnt_sample_done(struct kbase_device *kbdev)
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{
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unsigned long flags;
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_FAULT) {
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kbdev->hwcnt.backend.triggered = 1;
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wake_up(&kbdev->hwcnt.backend.wait);
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} else if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_DUMPING) {
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/* All finished and idle */
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_IDLE;
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kbdev->hwcnt.backend.triggered = 1;
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wake_up(&kbdev->hwcnt.backend.wait);
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}
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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}
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int kbase_instr_hwcnt_wait_for_dump(struct kbase_context *kctx)
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{
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struct kbase_device *kbdev = kctx->kbdev;
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unsigned long flags;
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int err;
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/* Wait for dump & cache clean to complete */
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wait_event(kbdev->hwcnt.backend.wait,
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kbdev->hwcnt.backend.triggered != 0);
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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if (kbdev->hwcnt.backend.state == KBASE_INSTR_STATE_FAULT) {
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err = -EINVAL;
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_IDLE;
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} else {
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/* Dump done */
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KBASE_DEBUG_ASSERT(kbdev->hwcnt.backend.state ==
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KBASE_INSTR_STATE_IDLE);
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err = 0;
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}
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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return err;
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}
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int kbase_instr_hwcnt_clear(struct kbase_context *kctx)
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{
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unsigned long flags;
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int err = -EINVAL;
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struct kbase_device *kbdev = kctx->kbdev;
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spin_lock_irqsave(&kbdev->hwcnt.lock, flags);
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/* Check it's the context previously set up and we're not already
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* dumping
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*/
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if (kbdev->hwcnt.kctx != kctx || kbdev->hwcnt.backend.state !=
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KBASE_INSTR_STATE_IDLE)
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goto out;
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/* Clear the counters */
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KBASE_KTRACE_ADD(kbdev, CORE_GPU_PRFCNT_CLEAR, NULL, 0);
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kbase_reg_write(kbdev, GPU_CONTROL_REG(GPU_COMMAND),
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GPU_COMMAND_PRFCNT_CLEAR);
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err = 0;
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out:
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spin_unlock_irqrestore(&kbdev->hwcnt.lock, flags);
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return err;
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}
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KBASE_EXPORT_SYMBOL(kbase_instr_hwcnt_clear);
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int kbase_instr_backend_init(struct kbase_device *kbdev)
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{
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spin_lock_init(&kbdev->hwcnt.lock);
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kbdev->hwcnt.backend.state = KBASE_INSTR_STATE_DISABLED;
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init_waitqueue_head(&kbdev->hwcnt.backend.wait);
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kbdev->hwcnt.backend.triggered = 0;
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#ifdef CONFIG_MALI_PRFCNT_SET_SELECT_VIA_DEBUG_FS
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/* Use the build time option for the override default. */
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#if defined(CONFIG_MALI_BIFROST_PRFCNT_SET_SECONDARY)
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kbdev->hwcnt.backend.override_counter_set = KBASE_HWCNT_SET_SECONDARY;
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#elif defined(CONFIG_MALI_PRFCNT_SET_TERTIARY)
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kbdev->hwcnt.backend.override_counter_set = KBASE_HWCNT_SET_TERTIARY;
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#else
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/* Default to primary */
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kbdev->hwcnt.backend.override_counter_set = KBASE_HWCNT_SET_PRIMARY;
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#endif
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#endif
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return 0;
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}
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void kbase_instr_backend_term(struct kbase_device *kbdev)
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{
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CSTD_UNUSED(kbdev);
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}
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#ifdef CONFIG_MALI_PRFCNT_SET_SELECT_VIA_DEBUG_FS
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void kbase_instr_backend_debugfs_init(struct kbase_device *kbdev)
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{
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/* No validation is done on the debugfs input. Invalid input could cause
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* performance counter errors. This is acceptable since this is a debug
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* only feature and users should know what they are doing.
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*
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* Valid inputs are the values accepted bythe SET_SELECT bits of the
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* PRFCNT_CONFIG register as defined in the architecture specification.
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*/
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debugfs_create_u8("hwcnt_set_select", S_IRUGO | S_IWUSR,
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kbdev->mali_debugfs_directory,
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(u8 *)&kbdev->hwcnt.backend.override_counter_set);
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}
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#endif
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