/*
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* Hitachi UL SolutionEngine 7343 FPGA IRQ Support.
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*
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* Copyright (C) 2008 Yoshihiro Shimoda
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* Copyright (C) 2012 Paul Mundt
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*
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* Based on linux/arch/sh/boards/se/7343/irq.c
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* Copyright (C) 2007 Nobuhiro Iwamatsu
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#define DRV_NAME "SE7343-FPGA"
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#define pr_fmt(fmt) DRV_NAME ": " fmt
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/irqdomain.h>
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#include <linux/io.h>
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#include <asm/sizes.h>
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#include <mach-se/mach/se7343.h>
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#define PA_CPLD_BASE_ADDR 0x11400000
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#define PA_CPLD_ST_REG 0x08 /* CPLD Interrupt status register */
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#define PA_CPLD_IMSK_REG 0x0a /* CPLD Interrupt mask register */
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static void __iomem *se7343_irq_regs;
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struct irq_domain *se7343_irq_domain;
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static void se7343_irq_demux(struct irq_desc *desc)
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{
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struct irq_data *data = irq_desc_get_irq_data(desc);
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struct irq_chip *chip = irq_data_get_irq_chip(data);
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unsigned long mask;
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int bit;
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chip->irq_mask_ack(data);
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mask = ioread16(se7343_irq_regs + PA_CPLD_ST_REG);
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for_each_set_bit(bit, &mask, SE7343_FPGA_IRQ_NR)
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generic_handle_irq(irq_linear_revmap(se7343_irq_domain, bit));
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chip->irq_unmask(data);
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}
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static void __init se7343_domain_init(void)
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{
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int i;
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se7343_irq_domain = irq_domain_add_linear(NULL, SE7343_FPGA_IRQ_NR,
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&irq_domain_simple_ops, NULL);
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if (unlikely(!se7343_irq_domain)) {
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printk("Failed to get IRQ domain\n");
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return;
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}
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for (i = 0; i < SE7343_FPGA_IRQ_NR; i++) {
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int irq = irq_create_mapping(se7343_irq_domain, i);
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if (unlikely(irq == 0)) {
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printk("Failed to allocate IRQ %d\n", i);
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return;
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}
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}
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}
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static void __init se7343_gc_init(void)
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{
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struct irq_chip_generic *gc;
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struct irq_chip_type *ct;
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unsigned int irq_base;
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irq_base = irq_linear_revmap(se7343_irq_domain, 0);
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gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7343_irq_regs,
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handle_level_irq);
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if (unlikely(!gc))
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return;
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ct = gc->chip_types;
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ct->chip.irq_mask = irq_gc_mask_set_bit;
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ct->chip.irq_unmask = irq_gc_mask_clr_bit;
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ct->regs.mask = PA_CPLD_IMSK_REG;
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irq_setup_generic_chip(gc, IRQ_MSK(SE7343_FPGA_IRQ_NR),
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IRQ_GC_INIT_MASK_CACHE,
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IRQ_NOREQUEST | IRQ_NOPROBE, 0);
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irq_set_chained_handler(IRQ0_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ1_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ4_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ4_IRQ, IRQ_TYPE_LEVEL_LOW);
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irq_set_chained_handler(IRQ5_IRQ, se7343_irq_demux);
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irq_set_irq_type(IRQ5_IRQ, IRQ_TYPE_LEVEL_LOW);
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}
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/*
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* Initialize IRQ setting
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*/
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void __init init_7343se_IRQ(void)
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{
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se7343_irq_regs = ioremap(PA_CPLD_BASE_ADDR, SZ_16);
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if (unlikely(!se7343_irq_regs)) {
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pr_err("Failed to remap CPLD\n");
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return;
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}
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/*
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* All FPGA IRQs disabled by default
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*/
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iowrite16(0, se7343_irq_regs + PA_CPLD_IMSK_REG);
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__raw_writew(0x2000, 0xb03fffec); /* mrshpc irq enable */
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se7343_domain_init();
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se7343_gc_init();
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}
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