/*
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* MPC8572 DS Core0 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts file allows core0 to have memory, l2, i2c, dma1, global-util, eth0,
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* eth1, crypto, pci0, pci1.
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/include/ "mpc8572ds.dts"
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
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cpus {
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PowerPC,8572@0 {
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};
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PowerPC,8572@1 {
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status = "disabled";
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};
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};
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localbus@ffe05000 {
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status = "disabled";
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};
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soc8572@ffe00000 {
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serial@4600 {
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status = "disabled";
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};
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dma@c300 {
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status = "disabled";
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};
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gpio-controller@f000 {
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};
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l2-cache-controller@20000 {
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cache-size = <0x80000>; // L2, 512K
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};
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ethernet@26000 {
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status = "disabled";
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};
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mdio@26520 {
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status = "disabled";
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};
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ethernet@27000 {
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status = "disabled";
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};
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mdio@27520 {
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status = "disabled";
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};
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pic@40000 {
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protected-sources = <
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31 32 33 37 38 39 /* enet2 enet3 */
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76 77 78 79 26 42 /* dma2 pci2 serial*/
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0xe4 0xe5 0xe6 0xe7 /* msi */
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>;
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};
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msi@41600 {
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msi-available-ranges = <0 0x80>;
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interrupts = <
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0xe0 0 0 0
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0xe1 0 0 0
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0xe2 0 0 0
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0xe3 0 0 0>;
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};
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timer@42100 {
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status = "disabled";
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};
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};
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pcie@ffe0a000 {
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status = "disabled";
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};
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};
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