/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_vp8e_vepu1_v2"
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#include <string.h>
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#include "mpp_mem.h"
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#include "mpp_rc.h"
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#include "mpp_common.h"
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#include "vp8e_syntax.h"
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#include "hal_vp8e_base.h"
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#include "hal_vp8e_vepu1_v2.h"
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#include "hal_vp8e_vepu1_reg.h"
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#include "hal_vp8e_debug.h"
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#define SWREG_AMOUNT_VEPU1 (164)
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#define HW_STATUS_MASK 0x58
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#define HW_STATUS_BUFFER_FULL 0x20
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#define HW_STATUS_FRAME_READY 0x04
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static MPP_RET vp8e_vpu_frame_start(void *hal)
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{
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RK_S32 i = 0;
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HalVp8eCtx *ctx = (HalVp8eCtx *) hal;
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Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
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Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *) ctx->regs;
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memset(regs, 0, sizeof(Vp8eVepu1Reg_t));
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regs->sw1.val = hw_cfg->irq_disable ? (regs->sw1.val | 0x02) :
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(regs->sw1.val & 0xfffffffd);
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if (hw_cfg->input_format < INPUT_RGB565)
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regs->sw2.val = 0xd00f;
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else if (hw_cfg->input_format < INPUT_RGB888)
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regs->sw2.val = 0xd00e;
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else
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regs->sw2.val = 0x900e;
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regs->sw5.base_stream = hw_cfg->output_strm_base;
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mpp_dev_set_reg_offset(ctx->dev, 5, hw_cfg->output_strm_offset);
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regs->sw6.base_control = hw_cfg->size_tbl_base;
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regs->sw14.nal_size_write = (hw_cfg->size_tbl_base != 0);
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regs->sw14.mv_write = (hw_cfg->mv_output_base != 0);
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regs->sw7.base_ref_lum = hw_cfg->internal_img_lum_base_r[0];
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regs->sw8.base_ref_chr = hw_cfg->internal_img_chr_base_r[0];
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regs->sw9.base_rec_lum = hw_cfg->internal_img_lum_base_w;
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regs->sw10.base_rec_chr = hw_cfg->internal_img_chr_base_w;
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regs->sw11.base_in_lum = hw_cfg->input_lum_base;
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regs->sw12.base_in_cb = hw_cfg->input_cb_base;
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mpp_dev_set_reg_offset(ctx->dev, 12, hw_cfg->input_cb_offset);
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regs->sw13.base_in_cr = hw_cfg->input_cr_base;
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mpp_dev_set_reg_offset(ctx->dev, 13, hw_cfg->input_cr_offset);
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regs->sw14.int_timeout = 1;
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regs->sw14.int_slice_ready = hw_cfg->int_slice_ready;
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regs->sw14.rec_write_disable = hw_cfg->rec_write_disable;
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regs->sw14.width = hw_cfg->mbs_in_row;
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regs->sw14.height = hw_cfg->mbs_in_col;
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regs->sw14.picture_type = hw_cfg->frame_coding_type;
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regs->sw14.encoding_mode = hw_cfg->coding_type;
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regs->sw15.chr_offset = hw_cfg->input_chroma_base_offset;
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regs->sw15.lum_offset = hw_cfg->input_luma_base_offset;
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regs->sw15.row_length = hw_cfg->pixels_on_row;
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regs->sw15.x_fill = hw_cfg->x_fill;
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regs->sw15.y_fill = hw_cfg->y_fill;
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regs->sw15.input_format = hw_cfg->input_format;
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regs->sw15.input_rot = hw_cfg->input_rotation;
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regs->sw18.cabac_enable = hw_cfg->enable_cabac;
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regs->sw18.ip_intra16_favor = hw_cfg->intra_16_favor;
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regs->sw21.inter_favor = hw_cfg->inter_favor;
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regs->sw18.disable_qp_mv = hw_cfg->disable_qp_mv;
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regs->sw18.deblocking = hw_cfg->filter_disable;
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regs->sw21.skip_penalty = hw_cfg->skip_penalty;
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regs->sw19.split_mv = hw_cfg->split_mv_mode;
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regs->sw20.split_penalty_16x8 = hw_cfg->split_penalty[0];
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regs->sw20.split_penalty_8x8 = hw_cfg->split_penalty[1];
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regs->sw20.split_penalty_8x4 = hw_cfg->split_penalty[2];
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regs->sw62.split_penalty4x4 = hw_cfg->split_penalty[3];
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regs->sw62.zero_mv_favor = hw_cfg->zero_mv_favor;
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regs->sw22.strm_hdr_rem1 = hw_cfg->strm_start_msb;
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regs->sw23.strm_hdr_rem2 = hw_cfg->strm_start_lsb;
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regs->sw24.strm_buf_limit = hw_cfg->output_strm_size;
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regs->sw16.base_ref_lum2 = hw_cfg->internal_img_lum_base_r[1];
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regs->sw17.base_ref_chr2 = hw_cfg->internal_img_chr_base_r[1];
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regs->sw27.y1_quant_dc = hw_cfg->y1_quant_dc[0];
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regs->sw28.y1_quant_ac = hw_cfg->y1_quant_ac[0];
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regs->sw29.y2_quant_dc = hw_cfg->y2_quant_dc[0];
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regs->sw30.y2_quant_ac = hw_cfg->y2_quant_ac[0];
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regs->sw31.ch_quant_dc = hw_cfg->ch_quant_dc[0];
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regs->sw32.ch_quant_ac = hw_cfg->ch_quant_ac[0];
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regs->sw27.y1_zbin_dc = hw_cfg->y1_zbin_dc[0];
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regs->sw28.y1_zbin_ac = hw_cfg->y1_zbin_ac[0];
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regs->sw29.y2_zbin_dc = hw_cfg->y2_zbin_dc[0];
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regs->sw30.y2_zbin_ac = hw_cfg->y2_zbin_ac[0];
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regs->sw31.ch_zbin_dc = hw_cfg->ch_zbin_dc[0];
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regs->sw32.ch_zbin_ac = hw_cfg->ch_zbin_ac[0];
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regs->sw27.y1_round_dc = hw_cfg->y1_round_dc[0];
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regs->sw28.y1_round_ac = hw_cfg->y1_round_ac[0];
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regs->sw29.y2_round_dc = hw_cfg->y2_round_dc[0];
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regs->sw30.y2_round_ac = hw_cfg->y2_round_ac[0];
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regs->sw31.ch_round_dc = hw_cfg->ch_round_dc[0];
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regs->sw32.ch_round_ac = hw_cfg->ch_round_ac[0];
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regs->sw33.y1_dequant_dc = hw_cfg->y1_dequant_dc[0];
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regs->sw33.y1_dequant_ac = hw_cfg->y1_dequant_ac[0];
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regs->sw33.y2_dequant_dc = hw_cfg->y2_dequant_dc[0];
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regs->sw34.y2_dequant_ac = hw_cfg->y2_dequant_ac[0];
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regs->sw34.ch_dequant_dc = hw_cfg->ch_dequant_dc[0];
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regs->sw34.ch_dequant_ac = hw_cfg->ch_dequant_ac[0];
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regs->sw33.mv_ref_idx = hw_cfg->mv_ref_idx[0];
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regs->sw34.mv_ref_idx2 = hw_cfg->mv_ref_idx[1];
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regs->sw34.ref2_enable = hw_cfg->ref2_enable;
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regs->sw35.bool_enc_value = hw_cfg->bool_enc_value;
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regs->sw36.bool_enc_value_bits = hw_cfg->bool_enc_value_bits;
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regs->sw36.bool_enc_range = hw_cfg->bool_enc_range;
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regs->sw36.filter_level = hw_cfg->filter_level[0];
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regs->sw36.golden_penalty = hw_cfg->golden_penalty;
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regs->sw36.filter_sharpness = hw_cfg->filter_sharpness;
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regs->sw36.dct_partition_count = hw_cfg->dct_partitions;
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regs->sw37.start_offset = hw_cfg->first_free_bit;
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regs->sw39.base_next_lum = hw_cfg->vs_next_luma_base;
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regs->sw40.stab_mode = hw_cfg->vs_mode;
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regs->sw19.dmv_penalty4p = hw_cfg->diff_mv_penalty[0];
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regs->sw19.dmv_penalty1p = hw_cfg->diff_mv_penalty[1];
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regs->sw19.dmv_penaltyqp = hw_cfg->diff_mv_penalty[2];
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regs->sw51.base_cabac_ctx = hw_cfg->cabac_tbl_base;
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regs->sw52.base_mv_write = hw_cfg->mv_output_base;
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regs->sw53.rgb_coeff_a = hw_cfg->rgb_coeff_a;
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regs->sw53.rgb_coeff_b = hw_cfg->rgb_coeff_b;
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regs->sw54.rgb_coeff_c = hw_cfg->rgb_coeff_c;
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regs->sw54.rgb_coeff_e = hw_cfg->rgb_coeff_e;
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regs->sw55.rgb_coeff_f = hw_cfg->rgb_coeff_f;
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regs->sw55.r_mask_msb = hw_cfg->r_mask_msb;
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regs->sw55.g_mask_msb = hw_cfg->g_mask_msb;
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regs->sw55.b_mask_msb = hw_cfg->b_mask_msb;
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regs->sw57.cir_start = hw_cfg->cir_start;
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regs->sw57.cir_interval = hw_cfg->cir_interval;
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regs->sw56.intra_area_left = hw_cfg->intra_area_left;
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regs->sw56.intra_area_right = hw_cfg->intra_area_right;
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regs->sw56.intra_area_top = hw_cfg->intra_area_top;
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regs->sw56.intra_area_bottom = hw_cfg->intra_area_bottom;
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regs->sw60.roi1_left = hw_cfg->roi1_left;
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regs->sw60.roi1_right = hw_cfg->roi1_right;
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regs->sw60.roi1_top = hw_cfg->roi1_top;
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regs->sw60.roi1_bottom = hw_cfg->roi1_bottom;
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regs->sw61.roi2_left = hw_cfg->roi2_left;
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regs->sw61.roi2_right = hw_cfg->roi2_right;
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regs->sw61.roi2_top = hw_cfg->roi2_top;
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regs->sw61.roi2_bottom = hw_cfg->roi2_bottom;
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regs->sw58.base_partition1 = hw_cfg->partition_Base[0];
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mpp_dev_set_reg_offset(ctx->dev, 58, hw_cfg->partition_offset[0]);
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regs->sw59.base_partition2 = hw_cfg->partition_Base[1];
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mpp_dev_set_reg_offset(ctx->dev, 59, hw_cfg->partition_offset[1]);
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regs->sw26.base_prob_count = hw_cfg->prob_count_base;
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regs->sw64.mode0_penalty = hw_cfg->intra_mode_penalty[0];
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regs->sw64.mode1_penalty = hw_cfg->intra_mode_penalty[1];
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regs->sw65.mode2_penalty = hw_cfg->intra_mode_penalty[2];
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regs->sw65.mode3_penalty = hw_cfg->intra_mode_penalty[3];
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for (i = 0; i < 5; i++) {
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regs->sw66_70[i].b_mode_0_penalty = hw_cfg->intra_b_mode_penalty[2 * i];
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regs->sw66_70[i].b_mode_1_penalty = hw_cfg->intra_b_mode_penalty[2 * i + 1];
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}
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regs->sw34.segment_enable = hw_cfg->segment_enable;
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regs->sw34.segment_map_update = hw_cfg->segment_map_update;
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regs->sw71.base_segment_map = hw_cfg->segment_map_base;
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for (i = 0; i < 3; i++) {
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regs->sw72_95[0 + i * 8].num_0.y1_quant_dc = hw_cfg->y1_quant_dc[1 + i];
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regs->sw72_95[0 + i * 8].num_0.y1_zbin_dc = hw_cfg->y1_zbin_dc[1 + i];
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regs->sw72_95[0 + i * 8].num_0.y1_round_dc = hw_cfg->y1_round_dc[1 + i];
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regs->sw72_95[1 + i * 8].num_1.y1_quant_ac = hw_cfg->y1_quant_ac[1 + i];
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regs->sw72_95[1 + i * 8].num_1.y1_zbin_ac = hw_cfg->y1_zbin_ac[1 + i];
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regs->sw72_95[1 + i * 8].num_1.y1_round_ac = hw_cfg->y1_round_ac[1 + i];
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regs->sw72_95[2 + i * 8].num_2.y2_quant_dc = hw_cfg->y2_quant_dc[1 + i];
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regs->sw72_95[2 + i * 8].num_2.y2_zbin_dc = hw_cfg->y2_zbin_dc[1 + i];
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regs->sw72_95[2 + i * 8].num_2.y2_round_dc = hw_cfg->y2_round_dc[1 + i];
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regs->sw72_95[3 + i * 8].num_3.y2_quant_ac = hw_cfg->y2_quant_ac[1 + i];
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regs->sw72_95[3 + i * 8].num_3.y2_zbin_ac = hw_cfg->y2_zbin_ac[1 + i];
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regs->sw72_95[3 + i * 8].num_3.y2_round_ac = hw_cfg->y2_round_ac[1 + i];
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regs->sw72_95[4 + i * 8].num_4.ch_quant_dc = hw_cfg->ch_quant_dc[1 + i];
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regs->sw72_95[4 + i * 8].num_4.ch_zbin_dc = hw_cfg->ch_zbin_dc[1 + i];
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regs->sw72_95[4 + i * 8].num_4.ch_round_dc = hw_cfg->ch_round_dc[1 + i];
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regs->sw72_95[5 + i * 8].num_5.ch_quant_ac = hw_cfg->ch_quant_ac[1 + i];
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regs->sw72_95[5 + i * 8].num_5.ch_zbin_ac = hw_cfg->ch_zbin_ac[1 + i];
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regs->sw72_95[5 + i * 8].num_5.ch_round_ac = hw_cfg->ch_round_ac[1 + i];
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regs->sw72_95[6 + i * 8].num_6.y1_dequant_dc = hw_cfg->y1_dequant_dc[1 + i];
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regs->sw72_95[6 + i * 8].num_6.y1_dequant_ac = hw_cfg->y1_dequant_ac[1 + i];
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regs->sw72_95[6 + i * 8].num_6.y2_dequant_dc = hw_cfg->y2_dequant_dc[1 + i];
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regs->sw72_95[7 + i * 8].num_7.y2_dequant_ac = hw_cfg->y2_dequant_ac[1 + i];
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regs->sw72_95[7 + i * 8].num_7.ch_dequant_dc = hw_cfg->ch_dequant_dc[1 + i];
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regs->sw72_95[7 + i * 8].num_7.ch_dequant_ac = hw_cfg->ch_dequant_ac[1 + i];
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regs->sw72_95[7 + i * 8].num_7.filter_level = hw_cfg->filter_level[1 + i];
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}
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regs->sw162.lf_ref_delta0 = hw_cfg->lf_ref_delta[0] & mask_7b;
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regs->sw162.lf_ref_delta1 = hw_cfg->lf_ref_delta[1] & mask_7b;
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regs->sw162.lf_ref_delta2 = hw_cfg->lf_ref_delta[2] & mask_7b;
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regs->sw162.lf_ref_delta3 = hw_cfg->lf_ref_delta[3] & mask_7b;
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regs->sw163.lf_mode_delta0 = hw_cfg->lf_mode_delta[0] & mask_7b;
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regs->sw163.lf_mode_delta1 = hw_cfg->lf_mode_delta[1] & mask_7b;
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regs->sw163.lf_mode_delta2 = hw_cfg->lf_mode_delta[2] & mask_7b;
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regs->sw163.lf_mode_delta3 = hw_cfg->lf_mode_delta[3] & mask_7b;
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RK_S32 j = 0;
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for (j = 0; j < 32; j++) {
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regs->sw96_127[j].penalty_0 = hw_cfg->dmv_penalty[j * 4 + 3];
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regs->sw96_127[j].penalty_1 = hw_cfg->dmv_penalty[j * 4 + 2];
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regs->sw96_127[j].penalty_2 = hw_cfg->dmv_penalty[j * 4 + 1];
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regs->sw96_127[j].penalty_3 = hw_cfg->dmv_penalty[j * 4];
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regs->sw128_159[j].qpel_penalty_0 = hw_cfg->dmv_qpel_penalty[j * 4 + 3];
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regs->sw128_159[j].qpel_penalty_1 = hw_cfg->dmv_qpel_penalty[j * 4 + 2];
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regs->sw128_159[j].qpel_penalty_2 = hw_cfg->dmv_qpel_penalty[j * 4 + 1];
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regs->sw128_159[j].qpel_penalty_3 = hw_cfg->dmv_qpel_penalty[j * 4];
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}
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regs->sw14.enable = 1;
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return MPP_OK;
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}
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static MPP_RET hal_vp8e_vepu1_init_v2(void *hal, MppEncHalCfg *cfg)
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{
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MPP_RET ret = MPP_OK;
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HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
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Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
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ctx->cfg = cfg->cfg;
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/* update output to MppEnc */
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cfg->type = VPU_CLIENT_VEPU1;
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ret = mpp_dev_init(&cfg->dev, cfg->type);
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if (ret) {
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mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
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return ret;
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}
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ctx->dev = cfg->dev;
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vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_init success.\n");
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ctx->buffers = mpp_calloc(Vp8eVpuBuf, 1);
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if (ctx->buffers == NULL) {
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mpp_err("failed to malloc buffers");
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return MPP_ERR_NOMEM;
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}
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ctx->buffer_ready = 0;
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ctx->frame_cnt = 0;
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ctx->frame_type = VP8E_FRM_KEY;
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ctx->prev_frame_lost = 0;
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ctx->frame_size = 0;
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ctx->reg_size = SWREG_AMOUNT_VEPU1;
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hw_cfg->irq_disable = 0;
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hw_cfg->rounding_ctrl = 0;
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hw_cfg->cp_distance_mbs = 0;
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hw_cfg->recon_img_id = 0;
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hw_cfg->input_lum_base = 0;
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hw_cfg->input_cb_base = 0;
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hw_cfg->input_cr_base = 0;
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hal_vp8e_init_qp_table(hal);
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return ret;
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}
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static MPP_RET hal_vp8e_vepu1_deinit_v2(void *hal)
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{
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MPP_RET ret = MPP_OK;
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HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
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hal_vp8e_buf_free(ctx);
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if (ctx->dev) {
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mpp_dev_deinit(ctx->dev);
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ctx->dev = NULL;
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}
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MPP_FREE(ctx->regs);
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MPP_FREE(ctx->buffers);
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vp8e_hal_dbg(VP8E_DBG_HAL_FUNCTION, "mpp_dev_deinit success.\n");
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return ret;
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}
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static MPP_RET hal_vp8e_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
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{
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MPP_RET ret = MPP_OK;
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HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
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ctx->rc->qp_hdr = MPP_CLIP3(0, 127, task->rc_task->info.quality_target);
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if (!ctx->buffer_ready) {
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ret = hal_vp8e_setup(hal);
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if (ret) {
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hal_vp8e_vepu1_deinit_v2(hal);
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mpp_err("failed to init hal vp8e\n");
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} else {
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ctx->buffer_ready = 1;
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}
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}
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memset(ctx->stream_size, 0, sizeof(ctx->stream_size));
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hal_vp8e_enc_strm_code(ctx, task);
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vp8e_vpu_frame_start(ctx);
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return MPP_OK;
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}
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static MPP_RET hal_vp8e_vepu1_start_v2(void *hal, HalEncTask *task)
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{
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MPP_RET ret = MPP_OK;
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HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
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if (VP8E_DBG_HAL_DUMP_REG & vp8e_hal_debug) {
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RK_U32 i = 0;
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RK_U32 *tmp = (RK_U32 *)ctx->regs;
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for (; i < ctx->reg_size; i++)
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mpp_log("reg[%d]:%x\n", i, tmp[i]);
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}
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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RK_U32 reg_size = ctx->reg_size * sizeof(RK_U32);
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wr_cfg.reg = ctx->regs;
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wr_cfg.size = reg_size;
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = ctx->regs;
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rd_cfg.size = reg_size;
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
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if (ret) {
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mpp_err_f("set register read failed %d\n", ret);
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break;
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}
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
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if (ret) {
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mpp_err_f("send cmd failed %d\n", ret);
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break;
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}
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} while (0);
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(void)task;
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return ret;
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}
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static void vp8e_update_hw_cfg(void *hal)
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{
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HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
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Vp8eHwCfg *hw_cfg = &ctx->hw_cfg;
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Vp8eVepu1Reg_t * regs = (Vp8eVepu1Reg_t *)ctx->regs;
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hw_cfg->output_strm_base = regs->sw24.strm_buf_limit / 8;
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hw_cfg->qp_sum = regs->sw25.qp_sum * 2;
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hw_cfg->mad_count = regs->sw38.mad_count;
|
hw_cfg->rlc_count = regs->sw37.rlc_sum * 4;
|
|
hw_cfg->intra_16_favor = -1;
|
hw_cfg->inter_favor = -1;
|
hw_cfg->diff_mv_penalty[0] = -1;
|
hw_cfg->diff_mv_penalty[1] = -1;
|
hw_cfg->diff_mv_penalty[2] = -1;
|
hw_cfg->skip_penalty = -1;
|
hw_cfg->golden_penalty = -1;
|
hw_cfg->split_penalty[0] = 0;
|
hw_cfg->split_penalty[1] = 0;
|
hw_cfg->split_penalty[3] = 0;
|
|
}
|
|
static MPP_RET hal_vp8e_vepu1_wait_v2(void *hal, HalEncTask *task)
|
{
|
MPP_RET ret;
|
HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
|
|
Vp8eFeedback *fb = &ctx->feedback;
|
Vp8eVepu1Reg_t *regs = (Vp8eVepu1Reg_t *)ctx->regs;
|
|
if (NULL == ctx->dev) {
|
mpp_err_f("invalid dev ctx\n");
|
return MPP_NOK;
|
}
|
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
|
if (ret)
|
mpp_err_f("poll cmd failed %d\n", ret);
|
|
fb->hw_status = regs->sw1.val & HW_STATUS_MASK;
|
if (regs->sw1.val & HW_STATUS_FRAME_READY)
|
vp8e_update_hw_cfg(ctx);
|
else if (regs->sw1.val & HW_STATUS_BUFFER_FULL)
|
ctx->bitbuf[1].size = 0;
|
|
hal_vp8e_update_buffers(ctx, task);
|
|
ctx->last_frm_intra = task->rc_task->frm.is_intra;
|
ctx->frame_cnt++;
|
|
task->rc_task->info.bit_real = ctx->frame_size << 3;
|
task->hw_length = task->length;
|
|
return ret;
|
}
|
|
static MPP_RET hal_vp8e_vepu1_get_task_v2(void *hal, HalEncTask *task)
|
{
|
HalVp8eCtx *ctx = (HalVp8eCtx *)hal;
|
Vp8eSyntax* syntax = (Vp8eSyntax*)task->syntax.data;
|
//ctx->cfg = syntax->cfg;
|
RK_U32 i;
|
|
for (i = 0; i < task->syntax.number; i++) {
|
if (syntax[i].type == VP8E_SYN_CFG) {
|
ctx->cfg = (MppEncCfgSet*)syntax[i].data;
|
}
|
if (syntax[i].type == VP8E_SYN_RC) {
|
ctx->rc = (Vp8eRc*) syntax[i].data;
|
}
|
}
|
|
ctx->frame_type = task->rc_task->frm.is_intra ? VP8E_FRM_KEY : VP8E_FRM_P;
|
|
return MPP_OK;
|
}
|
|
static MPP_RET hal_vp8e_vepu1_ret_task_v2(void *hal, HalEncTask *task)
|
{
|
(void)hal;
|
(void)task;
|
|
return MPP_OK;
|
}
|
|
const MppEncHalApi hal_vp8e_vepu1 = {
|
.name = "hal_vp8e_vepu1",
|
.coding = MPP_VIDEO_CodingVP8,
|
.ctx_size = sizeof(HalVp8eCtx),
|
.flag = 0,
|
.init = hal_vp8e_vepu1_init_v2,
|
.deinit = hal_vp8e_vepu1_deinit_v2,
|
.prepare = NULL,
|
.get_task = hal_vp8e_vepu1_get_task_v2,
|
.gen_regs = hal_vp8e_vepu1_gen_regs_v2,
|
.start = hal_vp8e_vepu1_start_v2,
|
.wait = hal_vp8e_vepu1_wait_v2,
|
.part_start = NULL,
|
.part_wait = NULL,
|
.ret_task = hal_vp8e_vepu1_ret_task_v2,
|
};
|
