/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_VP8E_VEPU1_REG_H__
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#define __HAL_VP8E_VEPU1_REG_H__
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#include "rk_type.h"
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typedef struct {
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RK_U32 sw0;
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struct {
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RK_U32 val : 32;
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} sw1;
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struct {
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RK_U32 val : 32;
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} sw2;
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RK_U32 sw3_4[2];
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struct {
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RK_U32 base_stream : 32;
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} sw5;
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struct {
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RK_U32 base_control : 32;
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} sw6;
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struct {
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RK_U32 base_ref_lum : 32;
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} sw7;
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struct {
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RK_U32 base_ref_chr : 32;
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} sw8;
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struct {
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RK_U32 base_rec_lum : 32;
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} sw9;
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struct {
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RK_U32 base_rec_chr : 32;
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} sw10;
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struct {
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RK_U32 base_in_lum : 32;
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} sw11;
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struct {
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RK_U32 base_in_cb : 32;
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} sw12;
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struct {
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RK_U32 base_in_cr : 32;
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} sw13;
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struct {
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RK_U32 enable : 1;
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RK_U32 encoding_mode : 2;
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RK_U32 picture_type : 2;
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RK_U32 : 1;
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RK_U32 rec_write_disable : 1;
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RK_U32 : 3;
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RK_U32 height : 9;
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RK_U32 width : 9;
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RK_U32 int_slice_ready : 1;
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RK_U32 nal_size_write : 1;
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RK_U32 mv_write : 1;
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RK_U32 int_timeout : 1;
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} sw14;
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struct {
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RK_U32 input_rot : 2;
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RK_U32 input_format : 4;
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RK_U32 y_fill : 4;
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RK_U32 x_fill : 2;
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RK_U32 row_length : 14;
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RK_U32 lum_offset : 3;
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RK_U32 chr_offset : 3;
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} sw15;
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struct {
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RK_U32 base_ref_lum2 : 32;
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} sw16;
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struct {
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RK_U32 base_ref_chr2 : 32;
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} sw17;
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struct {
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RK_U32 ip_intra16_favor : 16;
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RK_U32 stream_mode : 1;
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RK_U32 inter_4_restrict : 1;
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RK_U32 cabac_enable : 1;
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RK_U32 cabac_initidc : 2;
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RK_U32 transform_8x8 : 1;
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RK_U32 disable_qp_mv : 1;
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RK_U32 slice_size : 7;
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RK_U32 deblocking : 2;
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} sw18;
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struct {
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RK_U32 dmv_penalty1p : 10;
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RK_U32 dmv_penalty4p : 10;
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RK_U32 dmv_penaltyqp : 10;
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RK_U32 split_mv : 1;
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RK_U32 : 1;
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} sw19;
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struct {
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RK_U32 split_penalty_8x4 : 10;
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RK_U32 split_penalty_8x8 : 10;
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RK_U32 split_penalty_16x8 : 10;
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RK_U32 : 2;
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} sw20;
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struct {
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RK_U32 inter_favor : 16;
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RK_U32 num_slices_ready : 8;
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RK_U32 skip_penalty : 8;
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} sw21;
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struct {
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RK_U32 strm_hdr_rem1 : 32;
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} sw22;
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struct {
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RK_U32 strm_hdr_rem2 : 32;
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} sw23;
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struct {
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RK_U32 strm_buf_limit : 32;
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} sw24;
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struct {
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RK_U32 qp_sum : 21;
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RK_U32 : 1;
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RK_U32 mad_threshold : 6;
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RK_U32 mad_qp_delta : 4;
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} sw25;
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struct {
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RK_U32 base_prob_count : 32;
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} sw26;
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struct {
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RK_U32 y1_quant_dc : 14;
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RK_U32 y1_zbin_dc : 9;
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RK_U32 y1_round_dc : 8;
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RK_U32 : 1;
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} sw27;
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struct {
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RK_U32 y1_quant_ac : 14;
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RK_U32 y1_zbin_ac : 9;
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RK_U32 y1_round_ac : 8;
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RK_U32 : 1;
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} sw28;
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struct {
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RK_U32 y2_quant_dc : 14;
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RK_U32 y2_zbin_dc : 9;
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RK_U32 y2_round_dc : 8;
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RK_U32 : 1;
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} sw29;
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struct {
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RK_U32 y2_quant_ac : 14;
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RK_U32 y2_zbin_ac : 9;
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RK_U32 y2_round_ac : 8;
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RK_U32 : 1;
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} sw30;
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struct {
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RK_U32 ch_quant_dc : 14;
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RK_U32 ch_zbin_dc : 9;
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RK_U32 ch_round_dc : 8;
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RK_U32 : 1;
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} sw31;
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struct {
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RK_U32 ch_quant_ac : 14;
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RK_U32 ch_zbin_ac : 9;
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RK_U32 ch_round_ac : 8;
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RK_U32 : 1;
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} sw32;
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struct {
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RK_U32 y1_dequant_dc : 8;
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RK_U32 y1_dequant_ac : 9;
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RK_U32 y2_dequant_dc : 9;
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RK_U32 mv_ref_idx : 2;
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RK_U32 : 4;
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} sw33;
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struct {
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RK_U32 y2_dequant_ac : 9;
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RK_U32 ch_dequant_dc : 8;
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RK_U32 ch_dequant_ac : 9;
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RK_U32 mv_ref_idx2 : 2;
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RK_U32 ref2_enable : 1;
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RK_U32 segment_enable : 1;
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RK_U32 segment_map_update : 1;
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RK_U32 : 1;
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} sw34;
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struct {
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RK_U32 bool_enc_value : 32;
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} sw35;
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struct {
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RK_U32 bool_enc_range : 8;
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RK_U32 bool_enc_value_bits : 5;
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RK_U32 dct_partition_count : 2;
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RK_U32 filter_level : 6;
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RK_U32 filter_sharpness : 3;
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RK_U32 golden_penalty : 8;
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} sw36;
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struct {
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RK_U32 rlc_sum : 23;
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RK_U32 start_offset : 6;
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RK_U32 : 3;
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} sw37;
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struct {
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RK_U32 mb_count : 16;
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RK_U32 mad_count : 16;
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} sw38;
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struct {
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RK_U32 base_next_lum : 32;
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} sw39;
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struct {
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RK_U32 stab_minimum : 24;
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RK_U32 : 6;
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RK_U32 stab_mode : 2;
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} sw40;
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RK_U32 sw41_50[10];
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struct {
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RK_U32 base_cabac_ctx : 32;
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} sw51;
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struct {
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RK_U32 base_mv_write : 32;
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} sw52;
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struct {
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RK_U32 rgb_coeff_a : 16;
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RK_U32 rgb_coeff_b : 16;
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} sw53;
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struct {
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RK_U32 rgb_coeff_c : 16;
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RK_U32 rgb_coeff_e : 16;
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} sw54;
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struct {
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RK_U32 rgb_coeff_f : 16;
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RK_U32 r_mask_msb : 5;
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RK_U32 g_mask_msb : 5;
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RK_U32 b_mask_msb : 5;
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RK_U32 : 1;
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} sw55;
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struct {
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RK_U32 intra_area_bottom : 8;
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RK_U32 intra_area_top : 8;
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RK_U32 intra_area_right : 8;
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RK_U32 intra_area_left : 8;
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} sw56;
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struct {
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RK_U32 cir_interval : 16;
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RK_U32 cir_start : 16;
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} sw57;
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struct {
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RK_U32 base_partition1 : 32;
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} sw58;
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struct {
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RK_U32 base_partition2 : 32;
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} sw59;
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struct {
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RK_U32 roi1_bottom : 8;
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RK_U32 roi1_top : 8;
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RK_U32 roi1_right : 8;
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RK_U32 roi1_left : 8;
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} sw60;
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struct {
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RK_U32 roi2_bottom : 8;
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RK_U32 roi2_top : 8;
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RK_U32 roi2_right : 8;
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RK_U32 roi2_left : 8;
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} sw61;
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struct {
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RK_U32 roi2_delta_qp : 4;
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RK_U32 roi1_delta_qp : 4;
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RK_U32 mvc_inter_view_flag : 1;
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RK_U32 mvc_anchor_pic_flag : 1;
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RK_U32 mvc_temporal_id : 3;
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RK_U32 mvc_view_id : 3;
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RK_U32 mvc_priority_id : 3;
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RK_U32 split_penalty4x4 : 9;
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RK_U32 zero_mv_favor : 4;
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} sw62;
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RK_U32 sw63;
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struct {
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RK_U32 mode0_penalty : 12;
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RK_U32 mode1_penalty : 12;
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RK_U32 : 8;
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} sw64;
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struct {
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RK_U32 mode2_penalty : 12;
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RK_U32 mode3_penalty : 12;
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RK_U32 : 8;
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} sw65;
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struct {
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RK_U32 b_mode_0_penalty : 12;
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RK_U32 b_mode_1_penalty : 12;
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RK_U32 : 8;
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} sw66_70[5];
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struct {
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RK_U32 base_segment_map : 32;
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} sw71;
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union {
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struct {
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RK_U32 y1_quant_dc : 14;
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RK_U32 y1_zbin_dc : 9;
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RK_U32 y1_round_dc : 8;
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RK_U32 : 1;
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} num_0;
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struct {
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RK_U32 y1_quant_ac : 14;
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RK_U32 y1_zbin_ac : 9;
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RK_U32 y1_round_ac : 8;
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RK_U32 : 1;
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} num_1;
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struct {
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RK_U32 y2_quant_dc : 14;
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RK_U32 y2_zbin_dc : 9;
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RK_U32 y2_round_dc : 8;
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RK_U32 : 1;
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} num_2;
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struct {
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RK_U32 y2_quant_ac : 14;
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RK_U32 y2_zbin_ac : 9;
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RK_U32 y2_round_ac : 8;
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RK_U32 : 1;
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} num_3;
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struct {
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RK_U32 ch_quant_dc : 14;
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RK_U32 ch_zbin_dc : 9;
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RK_U32 ch_round_dc : 8;
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RK_U32 : 1;
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} num_4;
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struct {
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RK_U32 ch_quant_ac : 14;
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RK_U32 ch_zbin_ac : 9;
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RK_U32 ch_round_ac : 8;
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RK_U32 : 1;
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} num_5;
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struct {
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RK_U32 y1_dequant_dc : 8;
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RK_U32 y1_dequant_ac : 9;
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RK_U32 y2_dequant_dc : 9;
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RK_U32 : 6;
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} num_6;
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struct {
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RK_U32 y2_dequant_ac : 9;
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RK_U32 ch_dequant_dc : 8;
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RK_U32 ch_dequant_ac : 9;
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RK_U32 filter_level : 6;
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} num_7;
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} sw72_95[24];
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struct {
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RK_U32 penalty_0 : 8;
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RK_U32 penalty_1 : 8;
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RK_U32 penalty_2 : 8;
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RK_U32 penalty_3 : 8;
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} sw96_127[32];
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struct {
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RK_U32 qpel_penalty_0 : 8;
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RK_U32 qpel_penalty_1 : 8;
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RK_U32 qpel_penalty_2 : 8;
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RK_U32 qpel_penalty_3 : 8;
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} sw128_159[32];
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struct {
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RK_U32 cost_inter : 12;
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RK_U32 dmv_cost_const : 12;
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RK_U32 : 8;
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} sw160;
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struct {
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RK_U32 cost_golden_ref : 12;
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RK_U32 : 20;
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} sw161;
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struct {
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RK_U32 lf_ref_delta0 : 7; //vp8_loopfilter_intra
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RK_U32 lf_ref_delta1 : 7; //vp8_loopfilter_lastref
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RK_U32 lf_ref_delta2 : 7; //vp8_loopfilter_glodenref
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RK_U32 lf_ref_delta3 : 7; //vp8_loopfilter_alterf
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RK_U32 : 4;
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} sw162;
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struct {
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RK_U32 lf_mode_delta0 : 7; //vp8_loopfilter_bpred
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RK_U32 lf_mode_delta1 : 7; //vp8_loopfilter_zeromv
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RK_U32 lf_mode_delta2 : 7; //vp8_loopfilter_newmv
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RK_U32 lf_mode_delta3 : 7; //vp8_loopfilter_splitmv
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RK_U32 : 4;
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} sw163;
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} Vp8eVepu1Reg_t;
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#endif /*__HAL_VP8E_VEPU1_REG_H__*/
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