/*
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* Copyright 2017 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_m4vd_vdpu1"
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#include <stdio.h>
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#include <string.h>
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#include "mpp_mem.h"
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#include "mpp_env.h"
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#include "mpp_debug.h"
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#include "mpp_buffer.h"
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#include "mpp_common.h"
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#include "mpg4d_syntax.h"
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#include "hal_mpg4d_api.h"
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#include "hal_m4vd_com.h"
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#include "hal_m4vd_vdpu1.h"
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#include "hal_m4vd_vdpu1_reg.h"
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#include "mpp_dec_cb_param.h"
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static void vdpu1_mpg4d_setup_regs_by_syntax(hal_mpg4_ctx *ctx, MppSyntax syntax)
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{
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M4vdVdpu1Regs_t *regs = ctx->regs;
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DXVA2_DecodeBufferDesc **data = syntax.data;
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DXVA_PicParams_MPEG4_PART2 *pp = NULL;
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DXVA_QmatrixData *qm = NULL;
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RK_S32 mv_buf_fd = mpp_buffer_get_fd(ctx->mv_buf);
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RK_U32 stream_length = 0;
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RK_U32 stream_used = 0;
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RK_U32 i;
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for (i = 0; i < syntax.number; i++) {
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DXVA2_DecodeBufferDesc *desc = data[i];
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switch (desc->CompressedBufferType) {
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case DXVA2_PictureParametersBufferType : {
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pp = (DXVA_PicParams_MPEG4_PART2 *)desc->pvPVPState;
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} break;
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case DXVA2_InverseQuantizationMatrixBufferType : {
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qm = (DXVA_QmatrixData *)desc->pvPVPState;
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} break;
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case DXVA2_BitStreamDateBufferType : {
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stream_length = desc->DataSize;
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stream_used = desc->DataOffset;
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ctx->bitstrm_len = stream_length;
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} break;
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default : {
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mpp_err_f("found invalid buffer descriptor type %d\n", desc->CompressedBufferType);
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} break;
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}
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}
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mpp_assert(pp);
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mpp_assert(qm);
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mpp_assert(stream_length);
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mpp_assert(stream_used);
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// copy qp table to buffer
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{
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RK_U8 *dst = (RK_U8 *)mpp_buffer_get_ptr(ctx->qp_table);
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RK_U8 *src = (qm->bNewQmatrix[0]) ? (qm->Qmatrix[0]) : (default_intra_matrix);
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memcpy(dst, src, 64);
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dst += 64;
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src = (qm->bNewQmatrix[1]) ? (qm->Qmatrix[1]) : (default_inter_matrix);
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memcpy(dst, src, 64);
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}
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regs->SwReg04.sw_pic_mb_width = (pp->vop_width + 15) >> 4;
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regs->SwReg04.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4;
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if (pp->custorm_version == 4) {
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regs->SwReg04.sw_mb_width_off = pp->vop_width & 0xf;
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regs->SwReg04.sw_mb_height_off = pp->vop_height & 0xf;
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} else {
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regs->SwReg04.sw_mb_width_off = 0;
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regs->SwReg04.sw_mb_height_off = 0;
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}
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regs->SwReg03.sw_dec_mode = 1;
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/* note: When comparing bit 19 of reg136(that is sw_alt_scan_flag_e) with bit 6 of
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** reg120(that is sw_alt_scan_e), we may be confused about the function of
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** these two bits. According to C Model, just sw_alt_scan_flag_e is set,
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** but not sw_alt_scan_e.
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*/
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regs->SwReg18.sw_alt_scan_flag_e = pp->alternate_vertical_scan_flag;
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regs->SwReg48.sw_startmb_x = 0;
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regs->SwReg48.sw_startmb_y = 0;
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regs->SwReg03.sw_filtering_dis = 1;
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regs->SwReg18.sw_mpeg4_vc1_rc = pp->vop_rounding_type;
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regs->SwReg05.sw_intradc_vlc_thr = pp->intra_dc_vlc_thr;
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regs->SwReg06.sw_init_qp = pp->vop_quant;
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regs->SwReg05.sw_sync_markers_e = 1;
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{
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/*
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* update stream base address here according to consumed bit length
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* 1. hardware start address has to be 64 bit align
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* 2. hardware need to know which is the start bit in
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* 2. pass (10bit fd + (offset << 10)) register value to kernel
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*/
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RK_U32 val = regs->SwReg12.sw_rlc_vlc_base;
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RK_U32 consumed_bytes = stream_used >> 3;
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RK_U32 consumed_bytes_align = consumed_bytes & (~0x7);
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RK_U32 start_bit_offset = stream_used & 0x3F;
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RK_U32 left_bytes = stream_length - consumed_bytes_align;
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regs->SwReg12.sw_rlc_vlc_base = val;
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if (consumed_bytes_align)
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mpp_dev_set_reg_offset(ctx->dev, 12, consumed_bytes_align);
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regs->SwReg05.sw_strm_start_bit = start_bit_offset;
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regs->SwReg06.sw_stream_len = left_bytes;
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}
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regs->SwReg05.sw_vop_time_incr = pp->vop_time_increment_resolution;
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switch (pp->vop_coding_type) {
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case MPEG4_B_VOP : {
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RK_U32 time_bp = pp->time_bp;
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RK_U32 time_pp = pp->time_pp;
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RK_U32 trb_per_trd_d0 = MPP_DIV((((RK_S64)(1 * time_bp + 0)) << 27) + 1 * (time_pp - 1), time_pp);
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RK_U32 trb_per_trd_d1 = MPP_DIV((((RK_S64)(2 * time_bp + 1)) << 27) + 2 * (time_pp - 0), 2 * time_pp + 1);
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RK_U32 trb_per_trd_dm1 = MPP_DIV((((RK_S64)(2 * time_bp - 1)) << 27) + 2 * (time_pp - 1), 2 * time_pp - 1);
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regs->SwReg03.sw_pic_b_e = 1;
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regs->SwReg03.sw_pic_inter_e = 1;
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regs->SwReg18.sw_mpeg4_vc1_rc = 0;
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regs->SwReg14.sw_refer0_base = 1;
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mpp_assert(ctx->fd_ref1 >= 0);
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if (ctx->fd_ref1 >= 0) {
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regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref1;
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regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref1;
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} else {
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regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr;
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regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr;
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}
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mpp_assert(ctx->fd_ref0 >= 0);
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if (ctx->fd_ref0 >= 0) {
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regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_ref0;
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regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_ref0;
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} else {
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regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr;
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regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr;
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}
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regs->SwReg18.sw_fcode_fwd_hor = pp->vop_fcode_forward;
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regs->SwReg18.sw_fcode_fwd_ver = pp->vop_fcode_forward;
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regs->SwReg18.sw_fcode_bwd_hor = pp->vop_fcode_backward;
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regs->SwReg18.sw_fcode_bwd_ver = pp->vop_fcode_backward;
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regs->SwReg03.sw_write_mvs_e = 0;
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regs->SwReg41.sw_dir_mv_base = mv_buf_fd;
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regs->SwReg19.sw_refer5_base = trb_per_trd_d0;
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regs->SwReg21.sw_refer7_base = trb_per_trd_d1;
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regs->SwReg20.sw_refer6_base = trb_per_trd_dm1;
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} break;
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case MPEG4_P_VOP : {
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regs->SwReg03.sw_pic_b_e = 0;
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regs->SwReg03.sw_pic_inter_e = 1;
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if (ctx->fd_ref0 >= 0) {
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regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_ref0;
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regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_ref0;
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} else {
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regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr;
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regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr;
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}
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regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr;
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regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr;
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regs->SwReg18.sw_fcode_fwd_hor = pp->vop_fcode_forward;
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regs->SwReg18.sw_fcode_fwd_ver = pp->vop_fcode_forward;
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regs->SwReg03.sw_write_mvs_e = 1;
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regs->SwReg41.sw_dir_mv_base = mv_buf_fd;
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} break;
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case MPEG4_I_VOP : {
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regs->SwReg03.sw_pic_b_e = 0;
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regs->SwReg03.sw_pic_inter_e = 0;
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regs->SwReg14.sw_refer0_base = (RK_U32)ctx->fd_curr;
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regs->SwReg15.sw_refer1_base = (RK_U32)ctx->fd_curr;
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regs->SwReg16.sw_refer2_base = (RK_U32)ctx->fd_curr;
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regs->SwReg17.sw_refer3_base = (RK_U32)ctx->fd_curr;
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regs->SwReg03.sw_write_mvs_e = 0;
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regs->SwReg41.sw_dir_mv_base = mv_buf_fd;
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regs->SwReg18.sw_fcode_fwd_hor = 1;
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regs->SwReg18.sw_fcode_fwd_ver = 1;
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} break;
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default : {
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/* no nothing */
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} break;
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}
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if (pp->interlaced) {
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regs->SwReg03.sw_pic_interlace_e = 1;
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regs->SwReg03.sw_pic_fieldmode_e = 0;
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regs->SwReg04.sw_topfieldfirst_e = pp->top_field_first;
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}
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regs->SwReg18.sw_prev_anc_type = pp->prev_coding_type;
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regs->SwReg05.sw_type1_quant_e = pp->quant_type;
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regs->SwReg40.sw_qtable_base = mpp_buffer_get_fd(ctx->qp_table);
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regs->SwReg18.sw_mv_accuracy_fwd = pp->quarter_sample;
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}
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MPP_RET vdpu1_mpg4d_init(void *hal, MppHalCfg *cfg)
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{
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MPP_RET ret = MPP_OK;
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M4vdVdpu1Regs_t *regs = NULL;
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MppBufferGroup group = NULL;
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MppBuffer mv_buf = NULL;
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MppBuffer qp_table = NULL;
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hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
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mpp_assert(hal);
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ret = mpp_buffer_group_get_internal(&group, MPP_BUFFER_TYPE_ION);
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if (ret) {
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mpp_err_f("failed to get buffer group ret %d\n", ret);
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goto ERR_RET;
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}
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ret = mpp_buffer_get(group, &mv_buf, MPEG4_MAX_MV_BUF_SIZE);
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if (ret) {
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mpp_err_f("failed to get mv buffer ret %d\n", ret);
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goto ERR_RET;
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}
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ret = mpp_buffer_get(group, &qp_table, 64 * 2 * sizeof(RK_U8));
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if (ret) {
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mpp_err_f("failed to get qp talbe buffer ret %d\n", ret);
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goto ERR_RET;
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}
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regs = mpp_calloc(M4vdVdpu1Regs_t, 1);
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if (NULL == regs) {
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mpp_err_f("failed to malloc register ret\n");
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ret = MPP_ERR_MALLOC;
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goto ERR_RET;
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}
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ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1);
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if (ret) {
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mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
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goto ERR_RET;
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}
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ctx->frm_slots = cfg->frame_slots;
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ctx->pkt_slots = cfg->packet_slots;
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ctx->dec_cb = cfg->dec_cb;
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ctx->group = group;
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ctx->mv_buf = mv_buf;
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ctx->qp_table = qp_table;
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ctx->regs = regs;
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cfg->dev = ctx->dev;
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mpp_env_get_u32("hal_mpg4d_debug", &hal_mpg4d_debug, 0);
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return ret;
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ERR_RET:
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if (regs) {
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mpp_free(regs);
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regs = NULL;
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}
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if (qp_table) {
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mpp_buffer_put(qp_table);
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qp_table = NULL;
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}
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if (mv_buf) {
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mpp_buffer_put(mv_buf);
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mv_buf = NULL;
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}
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if (group) {
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mpp_buffer_group_put(group);
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group = NULL;
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}
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return ret;
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}
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MPP_RET vdpu1_mpg4d_deinit(void *hal)
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{
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MPP_RET ret = MPP_OK;
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hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
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mpp_assert(hal);
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if (ctx->regs) {
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mpp_free(ctx->regs);
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ctx->regs = NULL;
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}
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if (ctx->qp_table) {
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mpp_buffer_put(ctx->qp_table);
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ctx->qp_table = NULL;
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}
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if (ctx->mv_buf) {
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mpp_buffer_put(ctx->mv_buf);
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ctx->mv_buf = NULL;
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}
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if (ctx->group) {
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mpp_buffer_group_put(ctx->group);
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ctx->group = NULL;
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}
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if (ctx->dev) {
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mpp_dev_deinit(ctx->dev);
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ctx->dev = NULL;
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}
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return ret;
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}
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MPP_RET vdpu1_mpg4d_gen_regs(void *hal, HalTaskInfo *syn)
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{
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MPP_RET ret = MPP_OK;
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hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
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HalDecTask *task = &syn->dec;
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MppBuffer buf_frm_curr = NULL;
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MppBuffer buf_frm_ref0 = NULL;
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MppBuffer buf_frm_ref1 = NULL;
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MppBuffer buf_pkt = NULL;
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M4vdVdpu1Regs_t *regs = ctx->regs;
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mpp_assert(task->valid);
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mpp_assert(task->input >= 0);
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mpp_assert(task->output >= 0);
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memset(regs, 0, sizeof(M4vdVdpu1Regs_t));
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/*
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* basic register configuration setup here
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*/
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regs->SwReg02.sw_dec_out_endian = 1;
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regs->SwReg02.sw_dec_in_endian = 1;
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regs->SwReg02.sw_dec_inswap32_e = 1;
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regs->SwReg02.sw_dec_outswap32_e = 1;
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regs->SwReg02.sw_dec_strswap32_e = 1;
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regs->SwReg02.sw_dec_strendian_e = 1;
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regs->SwReg02.sw_dec_max_burst = 16;
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regs->SwReg55.sw_apf_threshold = 1;
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regs->SwReg02.sw_dec_timeout_e = 1;
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regs->SwReg02.sw_dec_clk_gate_e = 1;
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regs->SwReg01.sw_dec_en = 1;
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regs->SwReg49.sw_pred_bc_tap_0_0 = -1;
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regs->SwReg49.sw_pred_bc_tap_0_1 = 3;
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regs->SwReg49.sw_pred_bc_tap_0_2 = -6;
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regs->SwReg34.sw_pred_bc_tap_0_3 = 20;
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/* setup buffer for input / output / reference */
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mpp_buf_slot_get_prop(ctx->pkt_slots, task->input, SLOT_BUFFER, &buf_pkt);
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mpp_assert(buf_pkt);
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vpu_mpg4d_get_buffer_by_index(ctx, task->output, &buf_frm_curr);
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vpu_mpg4d_get_buffer_by_index(ctx, task->refer[0], &buf_frm_ref0);
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vpu_mpg4d_get_buffer_by_index(ctx, task->refer[1], &buf_frm_ref1);
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/* address registers setup first */
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ctx->fd_curr = mpp_buffer_get_fd(buf_frm_curr);
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ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1);
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ctx->fd_ref1 = (buf_frm_ref1) ? (mpp_buffer_get_fd(buf_frm_ref1)) : (-1);
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regs->SwReg13.dec_out_st_adr = (RK_U32)ctx->fd_curr;
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regs->SwReg12.sw_rlc_vlc_base = mpp_buffer_get_fd(buf_pkt);
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/* setup other registers, here will update packet address */
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vdpu1_mpg4d_setup_regs_by_syntax(ctx, task->syntax);
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/* memset tails to zero for stream buffer */
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{
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RK_U8 *ptr = (RK_U8 *)mpp_buffer_get_ptr(buf_pkt);
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RK_U32 strm_len = MPP_ALIGN(ctx->bitstrm_len, 16) + 64;
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memset(ptr + ctx->bitstrm_len, 0, strm_len - ctx->bitstrm_len);
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}
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return ret;
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}
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MPP_RET vdpu1_mpg4d_start(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
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RK_U32* regs = (RK_U32 *)ctx->regs;
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if (hal_mpg4d_debug & MPG4D_HAL_DBG_REG_PUT) {
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RK_U32 reg_count = (sizeof(M4vdVdpu1Regs_t) / sizeof(RK_U32));
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RK_U32 i = 0;
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for (i = 2; i < reg_count; i++) {
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mpp_log("reg[%03d]: %08x\n", i, regs[i]);
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}
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}
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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RK_U32 reg_size = sizeof(M4vdVdpu1Regs_t);
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wr_cfg.reg = regs;
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wr_cfg.size = reg_size;
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = regs;
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rd_cfg.size = reg_size;
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
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if (ret) {
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mpp_err_f("set register read failed %d\n", ret);
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break;
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}
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
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if (ret) {
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mpp_err_f("send cmd failed %d\n", ret);
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break;
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}
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} while (0);
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(void)task;
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return ret;
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}
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MPP_RET vdpu1_mpg4d_wait(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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hal_mpg4_ctx *ctx = (hal_mpg4_ctx *)hal;
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M4vdVdpu1Regs_t *regs = (M4vdVdpu1Regs_t *)ctx->regs;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
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if (ret)
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mpp_err_f("poll cmd failed %d\n", ret);
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if (hal_mpg4d_debug & MPG4D_HAL_DBG_REG_GET) {
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RK_U32 reg_count = (sizeof(M4vdVdpu1Regs_t) / sizeof(RK_U32));
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RK_U32 i = 0;
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for (i = 0; i < reg_count; i++) {
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mpp_log("reg[%03d]: %08x\n", i, ((RK_U32 *)regs)[i]);
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}
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}
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if (ctx->dec_cb) {
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DecCbHalDone param;
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param.task = (void *)&task->dec;
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param.regs = (RK_U32 *)ctx->regs;
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param.hard_err = !regs->SwReg01.sw_dec_rdy_int;
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mpp_callback(ctx->dec_cb, ¶m);
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}
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memset(®s->SwReg01, 0, sizeof(RK_U32));
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(void)task;
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return ret;
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}
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