/*
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* Copyright 2016 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_M2VD_VDPU2_REG_H__
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#define __HAL_M2VD_VDPU2_REG_H__
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#include "rk_type.h"
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extern RK_U32 m2vh_debug;
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#define M2VD_VDPU2_REG_NUM 159
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typedef struct M2vdVdpu2Reg_t {
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RK_U32 ppReg[50];
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struct {
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RK_U32 dec_out_tiled_e : 1;
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RK_U32 dec_latency : 6;
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RK_U32 pic_fixed_quant : 1;
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RK_U32 filtering_dis : 1;
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RK_U32 skip_mode : 1;
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RK_U32 dec_scmd_dis : 1;
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RK_U32 dec_adv_pre_dis : 1;
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RK_U32 priority_mode : 1; //chang
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RK_U32 refbu2_thr : 12;
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RK_U32 refbu2_picid : 5;
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RK_U32 reserve1 : 2;
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} sw50;
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struct {
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RK_U32 stream_len : 24;
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RK_U32 reserve1 : 1;
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RK_U32 init_qp : 6;
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RK_U32 reserve2 : 1;
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} sw51;
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struct {
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RK_U32 startmb_y : 8;
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RK_U32 startmb_x : 9;
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RK_U32 apf_threshold : 14;
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RK_U32 reserve : 1;
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} sw52;
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struct {
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RK_U32 sw_dec_mode;
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} sw53;
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struct {
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RK_U32 dec_in_endian : 1;
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RK_U32 dec_out_endian : 1;
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RK_U32 dec_inswap32_e : 1;
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RK_U32 dec_outswap32_e : 1;
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RK_U32 dec_strswap32_e : 1;
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RK_U32 dec_strendian_e : 1;
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RK_U32 reserve3 : 26;
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} sw54;
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struct {
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RK_U32 dec_irq : 1;
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RK_U32 dec_irq_dis : 1;
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RK_U32 reserve0 : 2;
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RK_U32 dec_rdy_int : 1;
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RK_U32 dec_bus_int : 1;
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RK_U32 dec_buffer_int : 1;
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RK_U32 reserve1 : 1;
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RK_U32 dec_aso_int : 1;
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RK_U32 dec_slice_int : 1;
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RK_U32 dec_pic_inf : 1;
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RK_U32 reserve2 : 1;
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RK_U32 dec_error_int : 1;
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RK_U32 dec_timeout : 1;
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RK_U32 reserve3 : 18;
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} sw55;
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struct {
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RK_U32 dec_axi_rn_id : 8;
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RK_U32 dec_axi_wr_id : 8;
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RK_U32 dec_max_burst : 5;
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RK_U32 resever : 1;
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RK_U32 dec_data_disc_e : 1;
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RK_U32 resever1 : 9;
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} sw56;
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struct {
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RK_U32 dec_e : 1;
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RK_U32 refbu2_buf_e : 1;
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RK_U32 dec_out_dis : 1;
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RK_U32 resever : 1;
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RK_U32 dec_clk_gate_e : 1;
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RK_U32 dec_timeout_e : 1;
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RK_U32 picord_count_e : 1;
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RK_U32 seq_mbaff_e : 1;
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RK_U32 reftopfirst_e : 1;
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RK_U32 ref_topfield_e : 1;
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RK_U32 write_mvs_e : 1;
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RK_U32 sorenson_e : 1;
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RK_U32 fwd_interlace_e : 1;
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RK_U32 pic_topfield_e : 1;
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RK_U32 pic_inter_e : 1;
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RK_U32 pic_b_e : 1;
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RK_U32 pic_fieldmode_e : 1;
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RK_U32 pic_interlace_e : 1;
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RK_U32 pjpeg_e : 1;
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RK_U32 divx3_e : 1;
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RK_U32 rlc_mode_e : 1;
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RK_U32 ch_8pix_ileav_e : 1;
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RK_U32 start_code_e : 1;
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RK_U32 resever1 : 8;
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RK_U32 dec_ahb_hlock_e : 1;
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} sw57;
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RK_U32 reserve0[3];
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struct {
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RK_U32 slice_table;
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} sw61;
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struct {
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RK_U32 directmv_reg;
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} sw62;
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struct {
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RK_U32 cur_pic_base;
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} sw63;
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struct {
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RK_U32 VLC_base;
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} sw64;
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RK_U32 reserve1[55];
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struct {
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RK_U32 ref_frames : 5;
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RK_U32 topfieldfirst_e : 1;
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RK_U32 alt_scan_e : 1;
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RK_U32 mb_height_off : 4;
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RK_U32 pic_mb_height_p : 8;
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RK_U32 mb_width_off : 4;
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RK_U32 pic_mb_width : 9;
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} sw120;
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RK_U32 reserve2;
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struct {
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RK_U32 frame_pred_dct : 1;
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RK_U32 intra_vlc_tab : 1;
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RK_U32 intra_dc_prec : 2;
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RK_U32 con_mv_e : 1;
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RK_U32 reserve : 19;
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RK_U32 qscale_type : 1;
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RK_U32 reserve1 : 1;
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RK_U32 stream_start_bit : 6;
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} sw122;
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RK_U32 reserve3[8];
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struct {
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RK_U32 ref0;
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} sw131;
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RK_U32 reserve4[2];
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struct {
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RK_U32 ref2;
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} sw134;
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struct {
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RK_U32 ref3;
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} sw135;
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struct {
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RK_U32 reserve : 1;
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RK_U32 mv_accuracy_bwd : 1;
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RK_U32 mv_accuracy_fwd : 1;
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RK_U32 fcode_bwd_ver : 4;
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RK_U32 fcode_bwd_hor : 4;
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RK_U32 fcode_fwd_ver : 4;
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RK_U32 fcode_fwd_hor : 4;
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RK_U32 alt_scan_flag_e : 1;
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RK_U32 reserve1 : 12;
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} sw136;
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RK_U32 reserve5[11];
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struct {
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RK_U32 ref1;
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} sw148;
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RK_U32 reserve6[10];
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} M2vdVdpu2Reg;
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#endif
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