/*
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* Copyright 2018 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_M2VD_VDPU1_REG_H__
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#define __HAL_M2VD_VDPU1_REG_H__
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#include "rk_type.h"
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#define M2VD_VDPU1_REG_NUM (101)
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typedef struct {
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struct {
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RK_U32 build_version : 3;
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RK_U32 product_IDen : 1;
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RK_U32 minor_version : 8;
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RK_U32 major_version : 4;
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RK_U32 product_numer : 16;
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} sw00;
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struct {
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RK_U32 dec_e : 1;
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RK_U32 reserve0 : 3;
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RK_U32 dec_irq_dis : 1;
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RK_U32 reserve1 : 3;
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RK_U32 dec_irq : 1;
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RK_U32 reserve2 : 3;
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RK_U32 dec_rdy_int : 1;
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RK_U32 dec_bus_int : 1;
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RK_U32 dec_buffer_int : 1;
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RK_U32 dec_aso_int : 1;
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RK_U32 dec_error_int : 1;
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RK_U32 dec_slice_int : 1;
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RK_U32 dec_timeout : 1;
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RK_U32 reserve3 : 5;
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RK_U32 dec_pic_inf : 1;
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RK_U32 reserve4 : 7;
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} sw01;
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struct {
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RK_U32 dec_max_burst : 5;
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RK_U32 dec_scmd_dis : 1;
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RK_U32 dec_adv_pre_dis : 1;
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RK_U32 priority_mode : 1; //chang
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RK_U32 dec_out_endian : 1;
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RK_U32 dec_in_endian : 1;
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RK_U32 dec_clk_gate_e : 1;
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RK_U32 dec_latency : 6;
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RK_U32 dec_out_tiled_e : 1;
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RK_U32 dec_data_disc_e : 1;
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RK_U32 dec_outswap32_e : 1;
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RK_U32 dec_inswap32_e : 1;
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RK_U32 dec_strendian_e : 1;
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RK_U32 dec_strswap32_e : 1;
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RK_U32 dec_timeout_e : 1;
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RK_U32 dec_axi_rn_id : 8;
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} sw02;
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struct {
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RK_U32 dec_axi_wr_id : 8;
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RK_U32 dec_ahb_hlock_e : 1;
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RK_U32 picord_count_e : 1;
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RK_U32 seq_mbaff_e : 1;
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RK_U32 reftopfirst_e : 1;
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RK_U32 write_mvs_e : 1;
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RK_U32 pic_fixed_quant : 1;
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RK_U32 filtering_dis : 1;
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RK_U32 dec_out_dis : 1;
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RK_U32 ref_topfield_e : 1;
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RK_U32 sorenson_e : 1;
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RK_U32 fwd_interlace_e : 1;
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RK_U32 pic_topfield_e : 1;
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RK_U32 pic_inter_e : 1;
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RK_U32 pic_b_e : 1;
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RK_U32 pic_fieldmode_e : 1;
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RK_U32 pic_interlace_e : 1;
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RK_U32 pjpeg_e : 1;
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RK_U32 divx3_e : 1;
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RK_U32 skip_mode : 1;
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RK_U32 rlc_mode_e : 1;
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RK_U32 dec_mode : 4;
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} sw03;
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struct {
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RK_U32 ref_frames : 5;
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RK_U32 topfieldfirst_e : 1;
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RK_U32 alt_scan_e : 1;
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RK_U32 mb_height_off : 4;
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RK_U32 pic_mb_height_p : 8;
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RK_U32 mb_width_off : 4;
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RK_U32 pic_mb_width : 9;
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} sw04;
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struct {
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RK_U32 frame_pred_dct : 1;
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RK_U32 intra_vlc_tab : 1;
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RK_U32 intra_dc_prec : 2;
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RK_U32 con_mv_e : 1;
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RK_U32 reserve : 19;
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RK_U32 qscale_type : 1;
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RK_U32 reserve1 : 1;
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RK_U32 stream_start_bit : 6;
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} sw05;
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struct {
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RK_U32 stream_len : 24;
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RK_U32 ch_8pix_ileav_e : 1;
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RK_U32 init_qp : 6;
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RK_U32 start_code_e : 1;
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} sw06;
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RK_U32 Reg07_11[5];
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struct {
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RK_U32 rlc_vlc_base : 32;
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} sw12;
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struct {
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RK_U32 dec_out_base : 32;
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} sw13;
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struct {
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RK_U32 refer0_base : 32;
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} sw14;
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struct {
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RK_U32 refer1_base : 32;
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} sw15;
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struct {
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RK_U32 refer2_base : 32;
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} sw16;
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struct {
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RK_U32 refer3_base : 32;
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} sw17;
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struct {
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RK_U32 reserve : 1;
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RK_U32 mv_accuracy_bwd : 1;
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RK_U32 mv_accuracy_fwd : 1;
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RK_U32 fcode_bwd_ver : 4;
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RK_U32 fcode_bwd_hor : 4;
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RK_U32 fcode_fwd_ver : 4;
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RK_U32 fcode_fwd_hor : 4;
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RK_U32 alt_scan_flag_e : 1;
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RK_U32 reserve1 : 12;
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} sw18;
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RK_U32 sw19_39[21];
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struct {
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RK_U32 qtable_base : 32;
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} sw40;
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struct {
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RK_U32 dir_mv_base : 32;
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} sw41;
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RK_U32 sw42_47[6];
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struct {
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RK_U32 reserve : 15;
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RK_U32 startmb_y : 8;
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RK_U32 startmb_x : 9;
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} sw48;
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RK_U32 sw49_50[2];
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struct {
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RK_U32 refbu_y_offset : 9;
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RK_U32 reserve0 : 3;
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RK_U32 refbu_fparmod_e : 1;
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RK_U32 refbu_eval_e : 1;
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RK_U32 refbu_picid : 5;
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RK_U32 refbu_thr : 12;
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RK_U32 refbu_e : 1;
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} sw51;
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struct {
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RK_U32 refbu_intra_sum : 16;
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RK_U32 refbu_hit_sum : 16;
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} sw52;
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RK_U32 sw53_54[2];
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struct {
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RK_U32 apf_threshold : 14;
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RK_U32 refbu2_picid : 5;
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RK_U32 refbu2_thr : 12;
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RK_U32 refbu2_buf_e : 1;
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} sw55;
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RK_U32 sw56_100[45];
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} M2vdVdpu1Reg_t;
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#endif // __HAL_M2VD_VDPU1_REG_H__
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