/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_m2vd_vdpu1"
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#include <string.h>
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#include "mpp_mem.h"
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#include "mpp_common.h"
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#include "hal_m2vd_base.h"
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#include "hal_m2vd_vdpu1_reg.h"
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#include "hal_m2vd_vpu1.h"
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MPP_RET hal_m2vd_vdpu1_init(void *hal, MppHalCfg *cfg)
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{
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MPP_RET ret = MPP_OK;
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M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
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M2vdVdpu1Reg_t *regs = NULL;
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regs = mpp_calloc(M2vdVdpu1Reg_t, 1);
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if (NULL == regs) {
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mpp_err_f("failed to malloc register ret\n");
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ret = MPP_ERR_MALLOC;
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goto __ERR_RET;
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}
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ctx->reg_len = M2VD_VDPU1_REG_NUM;
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ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU1);
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if (ret) {
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mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
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ret = MPP_ERR_UNKNOW;
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goto __ERR_RET;
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}
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if (ctx->group == NULL) {
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ret = mpp_buffer_group_get_internal(&ctx->group, MPP_BUFFER_TYPE_ION);
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if (ret) {
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mpp_err("m2v_hal mpp_buffer_group_get failed\n");
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goto __ERR_RET;
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}
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}
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ret = mpp_buffer_get(ctx->group, &ctx->qp_table, M2VD_BUF_SIZE_QPTAB);
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if (ret) {
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mpp_err("m2v_hal_qtable_base get buffer failed\n");
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goto __ERR_RET;
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}
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ctx->packet_slots = cfg->packet_slots;
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ctx->frame_slots = cfg->frame_slots;
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ctx->dec_cb = cfg->dec_cb;
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ctx->regs = (void*)regs;
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cfg->dev = ctx->dev;
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return ret;
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__ERR_RET:
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if (regs) {
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mpp_free(regs);
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regs = NULL;
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}
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if (ctx) {
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hal_m2vd_vdpu1_deinit(ctx);
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}
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return ret;
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}
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MPP_RET hal_m2vd_vdpu1_deinit(void *hal)
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{
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MPP_RET ret = MPP_OK;
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M2vdHalCtx *p = (M2vdHalCtx *)hal;
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if (p->dev) {
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mpp_dev_deinit(p->dev);
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p->dev = NULL;
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}
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if (p->qp_table) {
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ret = mpp_buffer_put(p->qp_table);
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p->qp_table = NULL;
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if (MPP_OK != ret) {
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mpp_err("m2v_hal qp_table put buffer failed\n");
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return ret;
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}
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}
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if (p->group) {
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ret = mpp_buffer_group_put(p->group);
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p->group = NULL;
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if (ret) {
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mpp_err("m2v_hal group free buffer failed\n");
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return ret;
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}
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}
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return ret;
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}
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static MPP_RET hal_m2vd_vdpu1_init_hwcfg(M2vdHalCtx *ctx)
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{
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M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t *)ctx->regs;
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memset(p_regs, 0, sizeof(M2vdVdpu1Reg_t));
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p_regs->sw02.dec_axi_rn_id = 0;
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p_regs->sw02.dec_timeout_e = 1;
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p_regs->sw02.dec_strswap32_e = 1;
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p_regs->sw02.dec_strendian_e = 1;
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p_regs->sw02.dec_inswap32_e = 1;
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p_regs->sw02.dec_outswap32_e = 1;
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p_regs->sw02.dec_clk_gate_e = 1;
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p_regs->sw02.dec_in_endian = 1;
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p_regs->sw02.dec_out_endian = 1;
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p_regs->sw02.dec_out_tiled_e = 0;
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p_regs->sw02.dec_max_burst = DEC_BUS_BURST_LENGTH_16;
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p_regs->sw02.dec_scmd_dis = 0;
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p_regs->sw02.dec_adv_pre_dis = 0;
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p_regs->sw55.apf_threshold = 8;
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p_regs->sw02.dec_latency = 0;
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p_regs->sw02.dec_data_disc_e = 0;
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p_regs->sw01.dec_irq = 0;
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p_regs->sw02.dec_axi_rn_id = 0;
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p_regs->sw03.dec_axi_wr_id = 0;
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p_regs->sw03.dec_mode = 8;
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return MPP_OK;
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}
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MPP_RET hal_m2vd_vdpu1_gen_regs(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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if (task->dec.valid) {
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void *q_table = NULL;
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MppBuffer streambuf = NULL;
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MppBuffer framebuf = NULL;
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M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
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M2VDDxvaParam *dx = (M2VDDxvaParam *)task->dec.syntax.data;
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M2vdVdpu1Reg_t *p_regs = (M2vdVdpu1Reg_t*) ctx->regs;
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task->dec.valid = 0;
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q_table = mpp_buffer_get_ptr(ctx->qp_table);
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memcpy(q_table, dx->qp_tab, M2VD_BUF_SIZE_QPTAB);
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hal_m2vd_vdpu1_init_hwcfg(ctx);
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p_regs->sw18.mv_accuracy_fwd = 1;
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p_regs->sw18.mv_accuracy_bwd = 1;
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if (dx->seq_ext_head_dec_flag) {
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p_regs->sw03.dec_mode = 5;
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p_regs->sw18.fcode_fwd_hor = dx->pic.full_pel_forward_vector;
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p_regs->sw18.fcode_fwd_ver = dx->pic.forward_f_code;
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p_regs->sw18.fcode_bwd_hor = dx->pic.full_pel_backward_vector;
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p_regs->sw18.fcode_bwd_ver = dx->pic.backward_f_code;
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} else {
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p_regs->sw03.dec_mode = 6;
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p_regs->sw18.fcode_fwd_hor = dx->pic.forward_f_code;
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p_regs->sw18.fcode_fwd_ver = dx->pic.forward_f_code;
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p_regs->sw18.fcode_bwd_hor = dx->pic.backward_f_code;
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p_regs->sw18.fcode_bwd_ver = dx->pic.backward_f_code;
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if (dx->pic.full_pel_forward_vector)
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p_regs->sw18.mv_accuracy_fwd = 0;
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if (dx->pic.full_pel_backward_vector)
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p_regs->sw18.mv_accuracy_bwd = 0;
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}
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p_regs->sw04.pic_mb_width = (dx->seq.decode_width + 15) >> 4;
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p_regs->sw04.pic_mb_height_p = (dx->seq.decode_height + 15) >> 4;
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p_regs->sw03.pic_interlace_e = 1 - dx->seq_ext.progressive_sequence;
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if (dx->pic_code_ext.picture_structure == M2VD_PIC_STRUCT_FRAME)
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p_regs->sw03.pic_fieldmode_e = 0;
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else {
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p_regs->sw03.pic_fieldmode_e = 1;
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p_regs->sw03.pic_topfield_e = dx->pic_code_ext.picture_structure == 1;
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}
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if (dx->pic.picture_coding_type == M2VD_CODING_TYPE_B)
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p_regs->sw03.pic_b_e = 1;
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else
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p_regs->sw03.pic_b_e = 0;
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if (dx->pic.picture_coding_type == M2VD_CODING_TYPE_I)
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p_regs->sw03.pic_inter_e = 0;
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else
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p_regs->sw03.pic_inter_e = 1;
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p_regs->sw04.topfieldfirst_e = dx->pic_code_ext.top_field_first;
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p_regs->sw03.fwd_interlace_e = 0;
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p_regs->sw03.write_mvs_e = 0;
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p_regs->sw04.alt_scan_e = dx->pic_code_ext.alternate_scan;
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p_regs->sw18.alt_scan_flag_e = dx->pic_code_ext.alternate_scan;
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p_regs->sw05.qscale_type = dx->pic_code_ext.q_scale_type;
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p_regs->sw05.intra_dc_prec = dx->pic_code_ext.intra_dc_precision;
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p_regs->sw05.con_mv_e = dx->pic_code_ext.concealment_motion_vectors;
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p_regs->sw05.intra_vlc_tab = dx->pic_code_ext.intra_vlc_format;
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p_regs->sw05.frame_pred_dct = dx->pic_code_ext.frame_pred_frame_dct;
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p_regs->sw06.init_qp = 1;
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mpp_buf_slot_get_prop(ctx->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
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p_regs->sw12.rlc_vlc_base = mpp_buffer_get_fd(streambuf);
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if (dx->bitstream_offset) {
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mpp_dev_set_reg_offset(ctx->dev, 12, dx->bitstream_offset);
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}
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mpp_buf_slot_get_prop(ctx->frame_slots, dx->CurrPic.Index7Bits, SLOT_BUFFER, &framebuf);
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if ((dx->pic_code_ext.picture_structure == M2VD_PIC_STRUCT_TOP_FIELD) ||
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(dx->pic_code_ext.picture_structure == M2VD_PIC_STRUCT_FRAME)) {
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p_regs->sw13.dec_out_base = mpp_buffer_get_fd(framebuf);
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} else {
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p_regs->sw13.dec_out_base = mpp_buffer_get_fd(framebuf);
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mpp_dev_set_reg_offset(ctx->dev, 13, MPP_ALIGN(dx->seq.decode_width, 16));
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}
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mpp_buf_slot_get_prop(ctx->frame_slots, dx->frame_refs[0].Index7Bits, SLOT_BUFFER, &framebuf);
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p_regs->sw14.refer0_base = mpp_buffer_get_fd(framebuf);
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mpp_buf_slot_get_prop(ctx->frame_slots, dx->frame_refs[1].Index7Bits, SLOT_BUFFER, &framebuf);
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p_regs->sw15.refer1_base = mpp_buffer_get_fd(framebuf);
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mpp_buf_slot_get_prop(ctx->frame_slots, dx->frame_refs[2].Index7Bits, SLOT_BUFFER, &framebuf);
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p_regs->sw16.refer2_base = mpp_buffer_get_fd(framebuf);
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mpp_buf_slot_get_prop(ctx->frame_slots, dx->frame_refs[3].Index7Bits, SLOT_BUFFER, &framebuf);
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p_regs->sw17.refer3_base = mpp_buffer_get_fd(framebuf);
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p_regs->sw40.qtable_base = mpp_buffer_get_fd(ctx->qp_table);
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p_regs->sw48.startmb_x = 0;
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p_regs->sw48.startmb_y = 0;
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p_regs->sw03.dec_out_dis = 0;
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p_regs->sw03.filtering_dis = 1;
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p_regs->sw06.stream_len = dx->bitstream_length;
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p_regs->sw05.stream_start_bit = dx->bitstream_start_bit;
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p_regs->sw01.dec_e = 1;
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task->dec.valid = 1;
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ctx->dec_frame_cnt++;
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}
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return ret;
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}
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MPP_RET hal_m2vd_vdpu1_start(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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RK_U32 *regs = (RK_U32 *)ctx->regs;
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RK_U32 reg_size = sizeof(M2vdVdpu1Reg_t);
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wr_cfg.reg = regs;
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wr_cfg.size = reg_size;
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = regs;
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rd_cfg.size = reg_size;
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
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if (ret) {
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mpp_err_f("set register read failed %d\n", ret);
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break;
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}
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
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if (ret) {
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mpp_err_f("send cmd failed %d\n", ret);
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break;
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}
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} while (0);
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(void)task;
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return ret;
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}
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MPP_RET hal_m2vd_vdpu1_wait(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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M2vdHalCtx *ctx = (M2vdHalCtx *)hal;
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M2vdVdpu1Reg_t* reg_out = (M2vdVdpu1Reg_t * )ctx->regs;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
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if (ret)
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mpp_err_f("poll cmd failed %d\n", ret);
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if (reg_out->sw01.dec_error_int | reg_out->sw01.dec_buffer_int) {
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if (ctx->dec_cb)
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mpp_callback(ctx->dec_cb, NULL);
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}
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(void)task;
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return ret;
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}
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