/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_jpege_vepu2"
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#include <string.h>
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#include "mpp_env.h"
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#include "mpp_common.h"
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#include "mpp_mem.h"
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#include "mpp_platform.h"
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#include "mpp_enc_hal.h"
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#include "vcodec_service.h"
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#include "hal_jpege_debug.h"
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#include "hal_jpege_api_v2.h"
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#include "hal_jpege_base.h"
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#define VEPU_JPEGE_VEPU2_NUM_REGS 184
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#define VEPU2_REG_INPUT_Y 48
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#define VEPU2_REG_INPUT_U 49
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#define VEPU2_REG_INPUT_V 50
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typedef struct jpege_vepu2_reg_set_t {
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RK_U32 val[VEPU_JPEGE_VEPU2_NUM_REGS];
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} jpege_vepu2_reg_set;
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MPP_RET hal_jpege_vepu2_init(void *hal, MppEncHalCfg *cfg)
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{
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MPP_RET ret = MPP_OK;
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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mpp_env_get_u32("hal_jpege_debug", &hal_jpege_debug, 0);
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hal_jpege_dbg_func("enter hal %p cfg %p\n", hal, cfg);
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/* update output to MppEnc */
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cfg->type = VPU_CLIENT_VEPU2;
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ret = mpp_dev_init(&cfg->dev, cfg->type);
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if (ret) {
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mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
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return ret;
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}
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ctx->dev = cfg->dev;
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jpege_bits_init(&ctx->bits);
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mpp_assert(ctx->bits);
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ret = hal_jpege_vepu_init_rc(&ctx->hal_rc);
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if (ret)
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return ret;
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ctx->cfg = cfg->cfg;
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ctx->reg_size = sizeof(RK_U32) * VEPU_JPEGE_VEPU2_NUM_REGS;
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ctx->regs = mpp_calloc_size(void, ctx->reg_size + EXTRA_INFO_SIZE);
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if (NULL == ctx->regs) {
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mpp_err_f("failed to malloc vepu2 regs\n");
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return MPP_NOK;
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}
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ctx->regs_out = mpp_calloc_size(void, ctx->reg_size + EXTRA_INFO_SIZE);
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if (NULL == ctx->regs_out) {
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mpp_err_f("failed to malloc vepu2 regs\n");
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return MPP_NOK;
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}
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hal_jpege_dbg_func("leave hal %p\n", hal);
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return MPP_OK;
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}
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MPP_RET hal_jpege_vepu2_deinit(void *hal)
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{
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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hal_jpege_dbg_func("enter hal %p\n", hal);
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if (ctx->bits) {
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jpege_bits_deinit(ctx->bits);
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ctx->bits = NULL;
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}
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if (ctx->dev) {
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mpp_dev_deinit(ctx->dev);
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ctx->dev = NULL;
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}
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hal_jpege_vepu_deinit_rc(&ctx->hal_rc);
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MPP_FREE(ctx->regs);
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MPP_FREE(ctx->regs_out);
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hal_jpege_dbg_func("leave hal %p\n", hal);
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return MPP_OK;
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}
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MPP_RET hal_jpege_vepu2_get_task(void *hal, HalEncTask *task)
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{
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
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hal_jpege_dbg_func("enter hal %p\n", hal);
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memcpy(&ctx->syntax, syntax, sizeof(ctx->syntax));
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/* Set rc paramters */
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hal_jpege_dbg_input("rc_mode %d\n", ctx->cfg->rc.rc_mode);
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if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
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if (!ctx->hal_rc.q_factor) {
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task->rc_task->info.quality_target = syntax->q_factor ? (100 - syntax->q_factor) : 80;
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task->rc_task->info.quality_min = 100 - syntax->qf_max;
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task->rc_task->info.quality_max = 100 - syntax->qf_min;
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task->rc_task->frm.is_intra = 1;
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} else {
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task->rc_task->info.quality_target = ctx->hal_rc.last_quality;
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task->rc_task->info.quality_min = 100 - syntax->qf_max;
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task->rc_task->info.quality_max = 100 - syntax->qf_min;
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}
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}
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ctx->hal_start_pos = mpp_packet_get_length(task->packet);
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/* prepare for part encoding */
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ctx->mcu_y = 0;
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ctx->mcu_h = syntax->mcu_h;
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ctx->sw_bit = 0;
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ctx->part_bytepos = 0;
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ctx->part_x_fill = 0;
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ctx->part_y_fill = 0;
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ctx->rst_marker_idx = 0;
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task->part_first = 1;
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task->part_last = 0;
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hal_jpege_dbg_func("leave hal %p\n", hal);
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return MPP_OK;
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}
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static MPP_RET hal_jpege_vepu2_set_extra_info(MppDev dev, JpegeSyntax *syntax,
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RK_U32 start_mbrow)
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{
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VepuOffsetCfg cfg;
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MppDevRegOffsetCfg trans_cfg;
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cfg.fmt = syntax->format;
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cfg.width = syntax->width;
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cfg.height = syntax->height;
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cfg.hor_stride = syntax->hor_stride;
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cfg.ver_stride = syntax->ver_stride;
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cfg.offset_x = syntax->offset_x;
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cfg.offset_y = syntax->offset_y + start_mbrow * 16;
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get_vepu_offset_cfg(&cfg);
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if (cfg.offset_byte[0]) {
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trans_cfg.reg_idx = VEPU2_REG_INPUT_Y;
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trans_cfg.offset = cfg.offset_byte[0];
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (cfg.offset_byte[1]) {
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trans_cfg.reg_idx = VEPU2_REG_INPUT_U;
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trans_cfg.offset = cfg.offset_byte[1];
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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if (cfg.offset_byte[2]) {
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trans_cfg.reg_idx = VEPU2_REG_INPUT_V;
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trans_cfg.offset = cfg.offset_byte[2];
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mpp_dev_ioctl(dev, MPP_DEV_REG_OFFSET, &trans_cfg);
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}
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return MPP_OK;
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}
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MPP_RET hal_jpege_vepu2_gen_regs(void *hal, HalEncTask *task)
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{
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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MppBuffer input = task->input;
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MppBuffer output = task->output;
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JpegeSyntax *syntax = &ctx->syntax;
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RK_U32 width = syntax->width;
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RK_U32 width_align = MPP_ALIGN(width, 16);
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RK_U32 height = syntax->height;
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MppFrameFormat fmt = syntax->format;
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RK_U32 hor_stride = 0;
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RK_U32 ver_stride = MPP_ALIGN(height, 16);
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JpegeBits bits = ctx->bits;
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RK_U32 *regs = (RK_U32 *)ctx->regs;
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size_t length = mpp_packet_get_length(task->packet);
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RK_U8 *buf = mpp_buffer_get_ptr(output);
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size_t size = mpp_buffer_get_size(output);
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const RK_U8 *qtable[2] = {NULL};
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RK_S32 bitpos;
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RK_S32 bytepos;
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RK_U32 x_fill = 0;
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RK_U32 y_fill = 0;
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VepuFormatCfg fmt_cfg;
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RK_U32 rotation = 0;
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hal_jpege_dbg_func("enter hal %p\n", hal);
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if (syntax->rotation == MPP_ENC_ROT_90)
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rotation = 1;
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else if (syntax->rotation == MPP_ENC_ROT_270)
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rotation = 2;
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else if (syntax->rotation != MPP_ENC_ROT_0)
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mpp_err_f("Warning: only support 90 or 270 degree rotate, request rotate %d", syntax->rotation);
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if (rotation) {
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MPP_SWAP(RK_U32, width, height);
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MPP_SWAP(RK_U32, width_align, ver_stride);
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}
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hor_stride = get_vepu_pixel_stride(&ctx->stride_cfg, width,
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syntax->hor_stride, fmt);
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//hor_stride must be align with 8, and ver_stride mus align with 2
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if ((hor_stride & 0x7) || (ver_stride & 0x1) || (hor_stride >= (1 << 15))) {
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mpp_err_f("illegal resolution, hor_stride %d, ver_stride %d, width %d, height %d\n",
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syntax->hor_stride, syntax->ver_stride,
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syntax->width, syntax->height);
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}
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x_fill = (width_align - width) / 4;
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y_fill = (ver_stride - height);
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mpp_assert(x_fill <= 3);
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mpp_assert(y_fill <= 15);
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ctx->part_x_fill = x_fill;
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ctx->part_y_fill = y_fill;
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/* write header to output buffer */
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jpege_bits_setup(bits, buf, (RK_U32)size);
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/* seek length bytes data */
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jpege_seek_bits(bits, length << 3);
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/* NOTE: write header will update qtable */
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if (ctx->cfg->rc.rc_mode != MPP_ENC_RC_MODE_FIXQP) {
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hal_jpege_vepu_rc(ctx, task);
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qtable[0] = ctx->hal_rc.qtable_y;
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qtable[1] = ctx->hal_rc.qtable_c;
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} else {
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qtable[0] = NULL;
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qtable[1] = NULL;
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}
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write_jpeg_header(bits, syntax, qtable);
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memset(regs, 0, sizeof(RK_U32) * VEPU_JPEGE_VEPU2_NUM_REGS);
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// input address setup
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regs[VEPU2_REG_INPUT_Y] = mpp_buffer_get_fd(input);
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regs[VEPU2_REG_INPUT_U] = regs[VEPU2_REG_INPUT_Y];
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regs[VEPU2_REG_INPUT_V] = regs[VEPU2_REG_INPUT_Y];
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// output address setup
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bitpos = jpege_bits_get_bitpos(bits);
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bytepos = (bitpos + 7) >> 3;
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ctx->base = buf;
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ctx->size = size;
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ctx->sw_bit = bitpos;
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ctx->part_bytepos = bytepos;
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get_msb_lsb_at_pos(®s[51], ®s[52], buf, bytepos);
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regs[53] = size - bytepos;
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// bus config
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regs[54] = 16 << 8;
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regs[60] = (((bytepos & 7) * 8) << 16) |
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(x_fill << 4) |
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(y_fill);
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regs[61] = hor_stride;
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regs[77] = mpp_buffer_get_fd(output);
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if (bytepos)
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mpp_dev_set_reg_offset(ctx->dev, 77, bytepos);
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/* 95 - 97 color conversion parameter */
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{
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RK_U32 coeffA;
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RK_U32 coeffB;
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RK_U32 coeffC;
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RK_U32 coeffE;
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RK_U32 coeffF;
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switch (syntax->color_conversion_type) {
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case 0 : { /* BT.601 */
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/*
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* Y = 0.2989 R + 0.5866 G + 0.1145 B
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* Cb = 0.5647 (B - Y) + 128
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* Cr = 0.7132 (R - Y) + 128
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*/
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coeffA = 19589;
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coeffB = 38443;
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coeffC = 7504;
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coeffE = 37008;
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coeffF = 46740;
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} break;
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case 1 : { /* BT.709 */
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/*
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* Y = 0.2126 R + 0.7152 G + 0.0722 B
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* Cb = 0.5389 (B - Y) + 128
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* Cr = 0.6350 (R - Y) + 128
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*/
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coeffA = 13933;
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coeffB = 46871;
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coeffC = 4732;
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coeffE = 35317;
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coeffF = 41615;
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} break;
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case 2 : {
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coeffA = syntax->coeffA;
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coeffB = syntax->coeffB;
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coeffC = syntax->coeffC;
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coeffE = syntax->coeffE;
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coeffF = syntax->coeffF;
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} break;
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default : {
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mpp_err("invalid color conversion type %d\n",
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syntax->color_conversion_type);
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coeffA = 19589;
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coeffB = 38443;
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coeffC = 7504;
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coeffE = 37008;
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coeffF = 46740;
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} break;
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}
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regs[95] = coeffA | (coeffB << 16);
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regs[96] = coeffC | (coeffE << 16);
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regs[97] = coeffF;
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}
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regs[103] = (width_align >> 4) << 8 |
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(ver_stride >> 4) << 20 |
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(1 << 6) | /* intra coding */
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(2 << 4) | /* format jpeg */
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1; /* encoder start */
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if (!get_vepu_fmt(&fmt_cfg, fmt)) {
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regs[74] = (fmt_cfg.format << 4) |
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(rotation << 2);
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regs[98] = (fmt_cfg.b_mask & 0x1f) << 16 |
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(fmt_cfg.g_mask & 0x1f) << 8 |
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(fmt_cfg.r_mask & 0x1f);
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regs[105] = 7 << 26 | (fmt_cfg.swap_32_in & 1) << 29 |
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(fmt_cfg.swap_16_in & 1) << 30 |
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(fmt_cfg.swap_8_in & 1) << 31;
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}
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regs[107] = ((syntax->part_rows & 0xff) << 16) |
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jpege_restart_marker[ctx->rst_marker_idx & 7];
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/* encoder interrupt */
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regs[109] = 1 << 12 | /* clock gating */
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1 << 10; /* enable timeout interrupt */
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if (syntax->low_delay) {
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/* slice encode end by RST */
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regs[107] |= (1 << 24);
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/* slice interrupt enable */
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regs[109] |= (1 << 16);
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}
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/* 0 ~ 31 quantization tables */
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{
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RK_S32 i;
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for (i = 0; i < 16; i++) {
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/* qtable need to reorder in particular order */
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regs[i] = qtable[0][qp_reorder_table[i * 4 + 0]] << 24 |
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qtable[0][qp_reorder_table[i * 4 + 1]] << 16 |
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qtable[0][qp_reorder_table[i * 4 + 2]] << 8 |
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qtable[0][qp_reorder_table[i * 4 + 3]];
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}
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for (i = 0; i < 16; i++) {
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/* qtable need to reorder in particular order */
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regs[i + 16] = qtable[1][qp_reorder_table[i * 4 + 0]] << 24 |
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qtable[1][qp_reorder_table[i * 4 + 1]] << 16 |
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qtable[1][qp_reorder_table[i * 4 + 2]] << 8 |
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qtable[1][qp_reorder_table[i * 4 + 3]];
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}
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}
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hal_jpege_dbg_func("leave hal %p\n", hal);
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return MPP_OK;
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}
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MPP_RET hal_jpege_vepu2_start(void *hal, HalEncTask *task)
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{
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MPP_RET ret = MPP_OK;
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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hal_jpege_dbg_func("enter hal %p\n", hal);
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hal_jpege_vepu2_set_extra_info(ctx->dev, &ctx->syntax, 0);
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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RK_U32 reg_size = ctx->reg_size;
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wr_cfg.reg = ctx->regs;
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wr_cfg.size = reg_size;
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = ctx->regs;
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rd_cfg.size = reg_size;
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
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if (ret) {
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mpp_err_f("set register read failed %d\n", ret);
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break;
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}
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
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if (ret) {
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mpp_err_f("send cmd failed %d\n", ret);
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break;
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}
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} while (0);
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hal_jpege_dbg_func("leave hal %p\n", hal);
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(void)task;
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return ret;
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}
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MPP_RET hal_jpege_vepu2_wait(void *hal, HalEncTask *task)
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{
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MPP_RET ret = MPP_OK;
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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JpegeBits bits = ctx->bits;
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RK_U32 *regs = ctx->regs;
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JpegeFeedback *feedback = &ctx->feedback;
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RK_U32 val;
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RK_U32 sw_bit = 0;
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RK_U32 hw_bit = 0;
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hal_jpege_dbg_func("enter hal %p\n", hal);
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if (ctx->dev) {
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
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if (ret)
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mpp_err_f("poll cmd failed %d\n", ret);
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}
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val = regs[109];
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hal_jpege_dbg_output("hw_status %08x\n", val);
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feedback->hw_status = val & 0x70;
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val = regs[53];
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sw_bit = jpege_bits_get_bitpos(bits);
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hw_bit = val;
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// NOTE: hardware will return 64 bit access byte count
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feedback->stream_length = ((sw_bit / 8) & (~0x7)) + hw_bit / 8;
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task->length = feedback->stream_length;
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task->hw_length = task->length - ctx->hal_start_pos;
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hal_jpege_dbg_output("stream bit: sw %d hw %d total %d hw_length %d\n",
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sw_bit, hw_bit, feedback->stream_length, task->hw_length);
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hal_jpege_dbg_func("leave hal %p\n", hal);
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return ret;
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}
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MPP_RET hal_jpege_vepu2_part_start(void *hal, HalEncTask *task)
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{
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MPP_RET ret = MPP_OK;
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HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
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JpegeSyntax *syntax = (JpegeSyntax *)task->syntax.data;
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RK_U32 mcu_w = syntax->mcu_w;
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RK_U32 mcu_h = syntax->mcu_h;
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RK_U32 mcu_y = ctx->mcu_y;
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RK_U32 part_mcu_h = syntax->part_rows;
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RK_U32 *regs = (RK_U32 *)ctx->regs;
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RK_U32 part_enc_h;
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RK_U32 part_enc_mcu_h;
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RK_U32 part_y_fill;
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RK_U32 part_not_end;
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hal_jpege_dbg_func("enter part start %p\n", hal);
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/* Fix register for each part encoding */
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task->part_first = !mcu_y;
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if (mcu_y + part_mcu_h < mcu_h) {
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part_enc_h = part_mcu_h * 16;
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part_enc_mcu_h = part_mcu_h;
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part_y_fill = 0;
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part_not_end = 1;
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task->part_last = 0;
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} else {
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part_enc_h = syntax->height - mcu_y * 16;
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part_enc_mcu_h = MPP_ALIGN(part_enc_h, 16) / 16;;
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part_y_fill = ctx->part_y_fill;
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part_not_end = 0;
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task->part_last = 1;
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}
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hal_jpege_dbg_detail("part first %d last %d\n", task->part_first, task->part_last);
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get_msb_lsb_at_pos(®s[51], ®s[52], ctx->base, ctx->part_bytepos);
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regs[53] = ctx->size - ctx->part_bytepos;
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regs[60] = (((ctx->part_bytepos & 7) * 8) << 16) |
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(ctx->part_x_fill << 4) |
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(part_y_fill);
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regs[77] = mpp_buffer_get_fd(task->output);
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if (ctx->part_bytepos)
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mpp_dev_set_reg_offset(ctx->dev, 77, ctx->part_bytepos);
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regs[103] = mcu_w << 8 |
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(part_enc_mcu_h) << 20 |
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(1 << 6) | /* intra coding */
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(2 << 4) | /* format jpeg */
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1; /* encoder start */
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regs[107] = part_not_end << 24 | jpege_restart_marker[ctx->rst_marker_idx & 7];
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ctx->rst_marker_idx++;
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hal_jpege_vepu2_set_extra_info(ctx->dev, syntax, mcu_y);
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ctx->mcu_y += part_enc_mcu_h;
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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RK_U32 reg_size = ctx->reg_size;
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wr_cfg.reg = ctx->regs;
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wr_cfg.size = reg_size;
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = ctx->regs_out;
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rd_cfg.size = reg_size;
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
|
if (ret) {
|
mpp_err_f("set register read failed %d\n", ret);
|
break;
|
}
|
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
|
if (ret) {
|
mpp_err_f("send cmd failed %d\n", ret);
|
break;
|
}
|
} while (0);
|
|
hal_jpege_dbg_func("leave part start %p\n", hal);
|
(void)task;
|
return ret;
|
}
|
|
MPP_RET hal_jpege_vepu2_part_wait(void *hal, HalEncTask *task)
|
{
|
MPP_RET ret = MPP_OK;
|
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
|
RK_U32 *regs = ctx->regs_out;
|
JpegeFeedback *feedback = &ctx->feedback;
|
RK_U32 hw_bit = 0;
|
|
hal_jpege_dbg_func("enter part wait %p\n", hal);
|
|
if (ctx->dev) {
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
|
if (ret)
|
mpp_err_f("poll cmd failed %d\n", ret);
|
}
|
|
hal_jpege_dbg_detail("hw_status %08x\n", regs[109]);
|
|
hw_bit = regs[53];
|
|
hal_jpege_dbg_detail("byte pos %d -> %d\n", ctx->part_bytepos,
|
(ctx->part_bytepos & (~7)) + (hw_bit / 8));
|
ctx->part_bytepos = (ctx->part_bytepos & (~7)) + (hw_bit / 8);
|
|
feedback->stream_length = ctx->part_bytepos;
|
task->length = ctx->part_bytepos;
|
task->hw_length = task->length - ctx->hal_start_pos;
|
|
hal_jpege_dbg_detail("stream_length %d, hw_byte %d",
|
feedback->stream_length, hw_bit / 8);
|
|
hal_jpege_dbg_output("stream bit: sw %d hw %d total %d hw_length %d\n",
|
ctx->sw_bit, hw_bit, feedback->stream_length, task->hw_length);
|
|
hal_jpege_dbg_func("leave part wait %p\n", hal);
|
return ret;
|
}
|
|
MPP_RET hal_jpege_vepu2_ret_task(void *hal, HalEncTask *task)
|
{
|
HalJpegeCtx *ctx = (HalJpegeCtx *)hal;
|
|
ctx->hal_rc.last_quality = task->rc_task->info.quality_target;
|
task->rc_task->info.bit_real = ctx->feedback.stream_length * 8;
|
task->hal_ret.data = &ctx->feedback;
|
task->hal_ret.number = 1;
|
|
return MPP_OK;
|
}
|
|
const MppEncHalApi hal_jpege_vepu2 = {
|
.name = "hal_jpege_vepu2",
|
.coding = MPP_VIDEO_CodingMJPEG,
|
.ctx_size = sizeof(HalJpegeCtx),
|
.flag = 0,
|
.init = hal_jpege_vepu2_init,
|
.deinit = hal_jpege_vepu2_deinit,
|
.prepare = NULL,
|
.get_task = hal_jpege_vepu2_get_task,
|
.gen_regs = hal_jpege_vepu2_gen_regs,
|
.start = hal_jpege_vepu2_start,
|
.wait = hal_jpege_vepu2_wait,
|
.part_start = hal_jpege_vepu2_part_start,
|
.part_wait = hal_jpege_vepu2_part_wait,
|
.ret_task = hal_jpege_vepu2_ret_task,
|
};
|
