/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_JPEGD_RKV_REG_H__
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#define __HAL_JPEGD_RKV_REG_H__
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#define JPEGD_REG_NUM (42)
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#define RKV_JPEGD_LITTLE_ENDIAN (0)
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#define RKV_JPEGD_BIG_ENDIAN (1)
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#define SCALEDOWN_DISABLE (0)
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#define SCALEDOWN_HALF (1)
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#define SCALEDOWN_QUARTER (2)
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#define SCALEDOWN_ONE_EIGHTS (3)
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#define OUTPUT_RASTER (0)
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#define OUTPUT_TILE (1)
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#define TIMEOUT_MODE_CYCLE_24 (0)
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#define TIMEOUT_MODE_CYCLE_18 (1)
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#define OUT_SEQUENCE_RASTER (0)
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#define OUT_SEQUENCE_TILE (1)
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#define YUV_TO_RGB_REC_BT601 (0)
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#define YUV_TO_RGB_REC_BT709 (1)
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#define YUV_TO_RGB_FULL_RANGE (1)
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#define YUV_TO_RGB_LIMIT_RANGE (0)
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#define YUV_OUT_FMT_NO_TRANS (0)
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#define YUV_OUT_FMT_2_RGB888 (1)
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#define YUV_OUT_FMT_2_RGB565 (2)
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// Not support YUV400 transmit to NV12
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#define YUV_OUT_FMT_2_NV12 (3)
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// Only support YUV422 or YUV444, YUV444 should scaledown uv
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#define YUV_OUT_FMT_2_YUYV (4)
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#define YUV_MODE_400 (0)
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#define YUV_MODE_411 (1)
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#define YUV_MODE_420 (2)
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#define YUV_MODE_422 (3)
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#define YUV_MODE_440 (4)
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#define YUV_MODE_444 (5)
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#define BIT_DEPTH_8 (0)
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#define BIT_DEPTH_12 (1)
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// No quantization/huffman table or table is the same as previous
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#define TBL_ENTRY_0 (0)
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// Grayscale picture with only 1 quantization/huffman table
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#define TBL_ENTRY_1 (1)
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// Common case, one table for luma, one for chroma
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#define TBL_ENTRY_2 (2)
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// 3 table entries, one for luma, one for cb, one for cr
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#define TBL_ENTRY_3 (3)
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// Restart interval marker disable
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#define RST_DISABLE (0)
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// Restart interval marker enable
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#define RST_ENABLE (1)
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typedef struct {
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struct {
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RK_U32 minor_ver : 8;
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RK_U32 bit_depth : 1;
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RK_U32 : 7;
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RK_U32 prod_num : 16;
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} reg0_id;
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struct {
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RK_U32 dec_e : 1;
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RK_U32 dec_irq_dis : 1;
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RK_U32 dec_timeout_e : 1;
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RK_U32 buf_empty_e : 1;
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RK_U32 buf_empty_reload_p : 1;
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RK_U32 soft_rst_en_p : 1;
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RK_U32 dec_irq_raw : 1;
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RK_U32 wait_reset_e : 1;
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RK_U32 dec_irq : 1;
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RK_U32 dec_rdy_sta : 1;
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RK_U32 dec_bus_sta : 1;
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RK_U32 dec_error_sta : 1;
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RK_U32 dec_timeout_sta : 1;
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RK_U32 dec_buf_empty_sta : 1;
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RK_U32 soft_rest_rdy : 1;
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RK_U32 buf_empty_force_end_flag : 1;
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RK_U32 care_strm_error_e : 1;
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RK_U32 : 15;
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} reg1_int;
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struct {
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RK_U32 in_endian : 1;
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RK_U32 in_swap32_e : 1;
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RK_U32 in_swap64_e : 1;
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RK_U32 str_endian : 1;
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RK_U32 str_swap32_e : 1;
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RK_U32 str_swap64_e : 1;
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RK_U32 out_endian : 1;
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RK_U32 out_swap32_e : 1;
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RK_U32 out_swap64_e : 1;
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RK_U32 out_cbcr_swap : 1;
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RK_U32 : 2;
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RK_U32 scaledown_mode : 2;
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RK_U32 : 2;
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RK_U32 time_out_mode : 1;
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RK_U32 force_softrest_valid : 1;
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RK_U32 : 2;
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RK_U32 fbc_e : 1;
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RK_U32 allow_16x8_cp_flag : 1;
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RK_U32 fbc_force_uncompress : 1;
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RK_U32 : 1;
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RK_U32 fill_down_e : 1;
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RK_U32 fill_right_e : 1;
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RK_U32 dec_out_sequence : 1;
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RK_U32 yuv_out_format : 3;
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RK_U32 yuv2rgb_rec : 1;
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RK_U32 yuv2rgb_range : 1;
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} reg2_sys;
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struct {
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RK_U32 pic_width_m1 : 16;
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RK_U32 pic_height_m1 : 16;
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} reg3_pic_size;
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struct {
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RK_U32 jpeg_mode : 3;
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RK_U32 : 1;
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RK_U32 pixel_depth : 3;
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RK_U32 : 1;
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RK_U32 qtables_sel : 2;
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RK_U32 : 2;
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RK_U32 htables_sel : 2;
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RK_U32 : 1;
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RK_U32 dri_e : 1;
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RK_U32 dri_mcu_num_m1 : 16;
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} reg4_pic_fmt;
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struct {
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RK_U32 y_hor_virstride : 16;
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RK_U32 uv_hor_virstride : 16;
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} reg5_hor_virstride;
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struct {
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RK_U32 : 4;
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RK_U32 y_virstride : 28;
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} reg6_y_virstride;
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struct {
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RK_U32 qtbl_len : 5;
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RK_U32 : 3;
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RK_U32 htbl_mincode_len : 5;
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RK_U32 : 3;
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RK_U32 htbl_value_len : 6;
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RK_U32 : 2;
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RK_U32 y_hor_virstride_h : 1;
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RK_U32 : 7;
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} reg7_tbl_len;
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struct {
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RK_U32 strm_start_byte : 4;
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RK_U32 stream_len : 28;
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} reg8_strm_len;
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RK_U32 reg9_qtbl_base; //64 bytes align
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RK_U32 reg10_htbl_mincode_base; //64 bytes align
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RK_U32 reg11_htbl_value_base; //64 bytes align
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RK_U32 reg12_strm_base; //16 bytes align
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RK_U32 reg13_dec_out_base; //64 bytes align
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struct {
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RK_U32 error_prc_mode : 1;
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RK_U32 strm_r0_err_mode : 2;
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RK_U32 strm_r1_err_mode : 2;
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RK_U32 strm_ffff_err_mode : 2;//default skip 0xffff
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RK_U32 strm_other_mark_mode : 2;
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RK_U32 strm_dri_seq_err_mode : 1;
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RK_U32 : 6;
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RK_U32 hfm_force_stop : 5;
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RK_U32 : 11;
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} reg14_strm_error;
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struct {
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RK_U32 strm_r0_marker : 8;
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RK_U32 strm_r0_mask : 8;
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RK_U32 strm_r1_marker : 8;
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RK_U32 strm_r1_mask : 8;
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} reg15_strm_mask;
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union {
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struct {
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RK_U32 dec_clkgate_e : 1;
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RK_U32 dec_strm_gate_e : 1;
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RK_U32 dec_huffman_gate_e : 1;
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RK_U32 dec_izq_gate_e : 1;
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RK_U32 dec_idct_gate_e : 1;
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RK_U32 busifd_gate_e : 1;
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RK_U32 post_prs_get_e : 1;
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RK_U32 dec_sram_gate_e : 1;
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RK_U32 : 24;
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};
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RK_U32 val;
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} reg16_clk_gate;
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RK_U32 reg17_29[13];
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struct {
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RK_U32 axi_per_work_e : 1;
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RK_U32 axi_per_clr_e : 1;
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RK_U32 axi_perf_frm_tyep : 1;
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RK_U32 axi_cnt_type : 1;
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RK_U32 rd_latency_id : 4;
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RK_U32 rd_latency_thr : 12;
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RK_U32 : 12;
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} reg30_perf_latency_ctrl0;
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struct {
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RK_U32 addr_align_type : 2;
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RK_U32 ar_cnt_id_type : 1;
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RK_U32 aw_cnt_id_type : 1;
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RK_U32 ar_count_id : 4;
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RK_U32 aw_count_id : 4;
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RK_U32 rd_totoal_bytes_mode : 1;
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RK_U32 : 19;
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} reg31_perf_latency_ctrl1;
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struct {
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RK_U32 mcu_pos_x : 16;
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RK_U32 mcu_pos_y : 16;
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} reg32_dbg_mcu_pos;
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struct {
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RK_U32 stream_dri_seq_err_sta : 1;
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RK_U32 stream_r0_err_sta : 1;
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RK_U32 stream_r1_err_sta : 1;
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RK_U32 stream_ffff_err_sta : 1;
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RK_U32 stream_other_mark_err_sta : 1;
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RK_U32 : 3;
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RK_U32 huffman_mcu_cnt_l : 1;
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RK_U32 huffman_mcu_cnt_m : 1;
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RK_U32 huffman_eoi_without_end : 1;
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RK_U32 huffman_end_without_eoi : 1;
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RK_U32 huffman_overflow : 1;
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RK_U32 huffman_buf_empty : 1;
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RK_U32 : 2;
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RK_U32 first_error_idx : 4;
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RK_U32 : 12;
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} regs33_dbg_error_info;
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struct {
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RK_U32 rd_max_latency_num_ch0 : 16;
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RK_U32 : 16;
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} reg34_perf_rd_max_latency_num0;
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RK_U32 reg35_perf_rd_latency_samp_num;
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RK_U32 reg36_perf_rd_latency_acc_sum;
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RK_U32 reg37_perf_rd_axi_total_byte;
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RK_U32 reg38_perf_wr_axi_total_byte;
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RK_U32 reg39_perf_working_cnt;
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struct {
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RK_U32 bus_status_flag : 19;
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RK_U32 : 13;
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} reg40_dbg_bus_sta;
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struct {
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RK_U32 work_status_flag : 18;
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RK_U32 : 12;
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} reg41_dbg_work_sta;
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} JpegRegSet;
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#endif /* __HAL_JPEGD_RKV_REG_H__ */
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