/*
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* Copyright 2017 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H264E_VEPU_V2_H__
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#define __HAL_H264E_VEPU_V2_H__
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#include "mpp_enc_cfg.h"
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#include "mpp_rc.h"
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#include "vepu_common.h"
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#define H264E_HAL_SET_REG(reg, addr, val) \
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do { \
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reg[(addr)>>2] = (RK_U32)(val); \
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if (hal_h264e_debug & 0/*H264E_HAL_LOG_INFO*/) \
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mpp_log("line(%d) set reg[%03d/%03x]: %08x", __LINE__, (addr)>>2, addr, val); \
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} while (0)
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typedef enum H264eVpuFrameType_t {
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H264E_VPU_FRAME_P = 0,
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H264E_VPU_FRAME_I = 1
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} H264eVpuFrameType;
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#define VEPU_CTRL_LEVELS 7
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#define VEPU_CHECK_POINTS_MAX 10
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typedef struct HalH264eVepuInput_t {
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/* Hardware config format */
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RK_S32 src_fmt;
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RK_S32 src_w;
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RK_S32 src_h;
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VepuStrideCfg stride_cfg;
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RK_S32 pixel_stride;
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size_t size_y;
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size_t size_c;
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RK_U32 offset_cb;
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RK_U32 offset_cr;
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RK_U8 r_mask_msb;
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RK_U8 g_mask_msb;
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RK_U8 b_mask_msb;
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RK_U8 swap_8_in;
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RK_U8 swap_16_in;
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RK_U8 swap_32_in;
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RK_U32 color_conversion_coeff_a;
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RK_U32 color_conversion_coeff_b;
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RK_U32 color_conversion_coeff_c;
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RK_U32 color_conversion_coeff_e;
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RK_U32 color_conversion_coeff_f;
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} HalH264eVepuPrep;
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typedef struct HalH264eVepuFrmAddr_t {
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// original frame Y/Cb/Cr/RGB address
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RK_U32 orig[3];
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// reconstruction frame
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RK_U32 recn[2];
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RK_U32 refr[2];
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} HalH264eVepuAddr;
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/*
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* Vepu buffer allocater
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* There are three internal buffer for Vepu encoder:
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* 1. cabac table input buffer
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* 2. nal size table output buffer
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* 3. recon / refer frame buffer
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*/
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typedef struct HalH264eVepuBufs_t {
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MppBufferGroup group;
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/* cabac table buffer */
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RK_S32 cabac_init_idc;
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MppBuffer cabac_table;
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/*
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* nal size table buffer
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* table size must be 64-bit multiple, space for zero at the end of table
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* Atleast 1 macroblock row in every slice
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*/
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RK_S32 mb_h;
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RK_S32 nal_tab_size;
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MppBuffer nal_size_table;
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/*
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* recon / refer frame buffer
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* sync with encoder using slot index
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*/
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size_t frm_size;
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size_t yuv_size;
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RK_S32 frm_cnt;
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MppBuffer frm_buf[H264E_MAX_REFS_CNT + 1];
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} HalH264eVepuBufs;
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typedef struct HalH264eVepuMbRc_t {
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/* VEPU MB rate control parameter for config to hardware */
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RK_S32 qp_init;
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RK_S32 qp_min;
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RK_S32 qp_max;
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/*
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* VEPU MB can have max 10 check points (cp).
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*
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* On each check point hardware will check the target bit and
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* error bits and change qp according to delta qp step
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*
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* cp_distance_mbs check point distance in mbs (0 = disabled)
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* cp_target bitrate target at each check point
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* cp_error error bit level step for each delta qp
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* cp_delta_qp delta qp applied on when on bit rate error amount
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*/
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RK_S32 cp_distance_mbs;
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RK_S32 cp_target[VEPU_CHECK_POINTS_MAX];
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RK_S32 cp_error[VEPU_CTRL_LEVELS];
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RK_S32 cp_delta_qp[VEPU_CTRL_LEVELS];
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/*
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* MAD based QP adjustment
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* mad_qp_change [-8..7]
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* mad_threshold MAD threshold div256
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*/
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RK_S32 mad_qp_change;
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RK_S32 mad_threshold;
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/* slice split by mb row (0 = one slice) */
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RK_S32 slice_size_mb_rows;
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/* favor and penalty for mode decision */
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/*
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* VEPU MB rate control parameter which is read from hardware
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* out_strm_size output stream size (bits)
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* qp_sum QP Sum div2 output
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* rlc_count RLC codeword count div4 output max 255*255*384/4
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*/
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RK_U32 hdr_strm_size;
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RK_U32 hdr_free_size;
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RK_U32 out_strm_size;
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RK_S32 qp_sum;
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RK_S32 rlc_count;
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RK_S32 cp_usage[VEPU_CHECK_POINTS_MAX];
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/* Macroblock count with MAD value under threshold output */
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RK_S32 less_mad_count;
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/* MB count output */
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RK_S32 mb_count;
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/* hardware encoding status 0 - corret 1 - error */
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RK_U32 hw_status;
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} HalH264eVepuMbRc;
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typedef void *HalH264eVepuMbRcCtx;
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typedef struct HalH264eVepuStreamAmend_t {
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RK_S32 enable;
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H264eSlice *slice;
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H264ePrefixNal *prefix;
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RK_S32 slice_enabled;
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RK_U8 *src_buf;
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RK_U8 *dst_buf;
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RK_S32 buf_size;
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MppPacket packet;
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RK_S32 buf_base;
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RK_S32 old_length;
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RK_S32 new_length;
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} HalH264eVepuStreamAmend;
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#ifdef __cplusplus
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extern "C" {
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#endif
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RK_S32 exp_golomb_signed(RK_S32 val);
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/* buffer management function */
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MPP_RET h264e_vepu_buf_init(HalH264eVepuBufs *bufs);
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MPP_RET h264e_vepu_buf_deinit(HalH264eVepuBufs *bufs);
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MPP_RET h264e_vepu_buf_set_cabac_idc(HalH264eVepuBufs *bufs, RK_S32 idc);
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MPP_RET h264e_vepu_buf_set_frame_size(HalH264eVepuBufs *bufs, RK_S32 w, RK_S32 h);
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MppBuffer h264e_vepu_buf_get_nal_size_table(HalH264eVepuBufs *bufs);
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MppBuffer h264e_vepu_buf_get_frame_buffer(HalH264eVepuBufs *bufs, RK_S32 index);
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/* preprocess setup function */
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MPP_RET h264e_vepu_prep_setup(HalH264eVepuPrep *prep, MppEncPrepCfg *cfg);
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MPP_RET h264e_vepu_prep_get_addr(HalH264eVepuPrep *prep, MppBuffer buffer,
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RK_U32 (*addr)[3]);
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/* macroblock bitrate control function */
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MPP_RET h264e_vepu_mbrc_init(HalH264eVepuMbRcCtx *ctx, HalH264eVepuMbRc *mbrc);
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MPP_RET h264e_vepu_mbrc_deinit(HalH264eVepuMbRcCtx ctx);
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MPP_RET h264e_vepu_mbrc_setup(HalH264eVepuMbRcCtx ctx, MppEncCfgSet *cfg);
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MPP_RET h264e_vepu_slice_split_cfg(H264eSlice *slice, HalH264eVepuMbRc *mbrc,
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EncRcTask *rc_task, MppEncCfgSet *set_cfg);
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/*
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* generate hardware MB rc config by:
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* 1 - HalH264eVepuMbRcCtx ctx
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* The previous frame encoding status
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* 2 - RcSyntax
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* Provide current frame target bitrate related info
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* 3 - EncFrmStatus
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* Provide dpb related info like I / P frame, temporal id, refer distance
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*
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* Then output the HalH264eVepuMbRc for register generation
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*/
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MPP_RET h264e_vepu_mbrc_prepare(HalH264eVepuMbRcCtx ctx, HalH264eVepuMbRc *mbrc,
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EncRcTask *rc_task);
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MPP_RET h264e_vepu_mbrc_update(HalH264eVepuMbRcCtx ctx, HalH264eVepuMbRc *mbrc);
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MPP_RET h264e_vepu_stream_amend_init(HalH264eVepuStreamAmend *ctx);
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MPP_RET h264e_vepu_stream_amend_deinit(HalH264eVepuStreamAmend *ctx);
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MPP_RET h264e_vepu_stream_amend_config(HalH264eVepuStreamAmend *ctx,
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MppPacket packet, MppEncCfgSet *cfg,
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H264eSlice *slice, H264ePrefixNal *prefix);
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MPP_RET h264e_vepu_stream_amend_proc(HalH264eVepuStreamAmend *ctx);
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MPP_RET h264e_vepu_stream_amend_sync_ref_idc(HalH264eVepuStreamAmend *ctx);
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#ifdef __cplusplus
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}
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#endif
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#endif
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