/*
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* Copyright 2017 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H264E_VEPU1_REG_TBL_H__
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#define __HAL_H264E_VEPU1_REG_TBL_H__
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#include "rk_type.h"
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#define BIT(n) (1<<(n))
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/* RK3288 Encoder registers. */
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#define VEPU_REG_INTERRUPT 0x004
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#define VEPU_REG_INTERRUPT_SLICE_READY BIT(8)
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#define VEPU_REG_INTERRUPT_TIMEOUT BIT(6)
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#define VEPU_REG_INTERRUPT_BUFFER_FULL BIT(5)
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#define VEPU_REG_INTERRUPT_RESET BIT(4)
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#define VEPU_REG_INTERRUPT_BUS_ERROR BIT(3)
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#define VEPU_REG_INTERRUPT_FRAME_READY BIT(2)
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#define VEPU_REG_INTERRUPT_DIS_BIT BIT(1)
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#define VEPU_REG_INTERRUPT_BIT BIT(0)
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#define VEPU_REG_AXI_CTRL 0x008
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#define VEPU_REG_AXI_CTRL_WRITE_ID(x) (((x) & 0xff) << 24)
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#define VEPU_REG_AXI_CTRL_READ_ID(x) (((x) & 0xff) << 16)
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#define VEPU_REG_OUTPUT_SWAP16 BIT(15)
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#define VEPU_REG_INPUT_SWAP16 BIT(14)
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#define VEPU_REG_INPUT_SWAP16_(x) (((x) & 1) << 14)
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#define VEPU_REG_AXI_CTRL_BURST_LEN(x) (((x) & 0x3f) << 8)
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#define VEPU_REG_AXI_CTRL_BURST_DISABLE BIT(7)
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#define VEPU_REG_AXI_CTRL_INCREMENT_MODE BIT(6)
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#define VEPU_REG_AXI_CTRL_BURST_DISCARD BIT(5)
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#define VEPU_REG_CLK_GATING_EN BIT(4)
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#define VEPU_REG_OUTPUT_SWAP32 BIT(3)
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#define VEPU_REG_INPUT_SWAP32 BIT(2)
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#define VEPU_REG_INPUT_SWAP32_(x) (((x) & 1) << 2)
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#define VEPU_REG_OUTPUT_SWAP8 BIT(1)
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#define VEPU_REG_INPUT_SWAP8 BIT(0)
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#define VEPU_REG_INPUT_SWAP8_(x) ((x) & 1)
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#define VEPU_REG_ADDR_OUTPUT_STREAM 0x014
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#define VEPU_REG_ADDR_OUTPUT_CTRL 0x018
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#define VEPU_REG_ADDR_REF_LUMA 0x01c
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#define VEPU_REG_ADDR_REF_CHROMA 0x020
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#define VEPU_REG_ADDR_REC_LUMA 0x024
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#define VEPU_REG_ADDR_REC_CHROMA 0x028
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#define VEPU_REG_ADDR_IN_LUMA 0x02c
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#define VEPU_REG_ADDR_IN_CB 0x030
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#define VEPU_REG_ADDR_IN_CR 0x034
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#define VEPU_REG_ENCODE_CTRL 0x038
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#define VEPU_REG_INTERRUPT_TIMEOUT_EN BIT(31)
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#define VEPU_REG_MV_WRITE_EN BIT(30)
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#define VEPU_REG_SIZE_TABLE_PRESENT BIT(29)
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#define VEPU_REG_INTERRUPT_SLICE_READY_EN BIT(28)
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#define VEPU_REG_MB_WIDTH(x) (((x) & 0x1ff) << 19)
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#define VEPU_REG_MB_HEIGHT(x) (((x) & 0x1ff) << 10)
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#define VEPU_REG_RECON_WRITE_DIS BIT(6)
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#define VEPU_REG_PIC_TYPE(x) (((x) & 0x3) << 3)
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#define VEPU_REG_ENCODE_FORMAT(x) (((x) & 0x3) << 1)
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#define VEPU_REG_ENCODE_ENABLE BIT(0)
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#define VEPU_REG_ENC_INPUT_IMAGE_CTRL 0x03c
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#define VEPU_REG_IN_IMG_CHROMA_OFFSET(x) (((x) & 0x7) << 29)
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#define VEPU_REG_IN_IMG_LUMA_OFFSET(x) (((x) & 0x7) << 26)
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#define VEPU_REG_IN_IMG_CTRL_ROW_LEN(x) (((x) & 0x3fff) << 12)
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#define VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(x) (((x) & 0x3) << 10)
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#define VEPU_REG_IN_IMG_CTRL_OVRFLB(x) (((x) & 0xf) << 6)
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#define VEPU_REG_IN_IMG_CTRL_FMT(x) (((x) & 0xf) << 2)
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#define VEPU_REG_IN_IMG_ROTATE_MODE(x) (((x) & 0x3) << 0)
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#define VEPU_REG_ENC_CTRL0 0x040
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#define VEPU_REG_PPS_INIT_QP(x) (((x) & 0x3f) << 26)
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#define VEPU_REG_SLICE_FILTER_ALPHA(x) (((x) & 0xf) << 22)
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#define VEPU_REG_SLICE_FILTER_BETA(x) (((x) & 0xf) << 18)
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#define VEPU_REG_CHROMA_QP_OFFSET(x) (((x) & 0x1f) << 13)
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#define VEPU_REG_IDR_PIC_ID(x) (((x) & 0xf) << 1)
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#define VEPU_REG_CONSTRAINED_INTRA_PREDICTION BIT(0)
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#define VEPU_REG_ENC_CTRL1 0x044
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#define VEPU_REG_PPS_ID(x) (((x) & 0xff) << 24)
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#define VEPU_REG_INTRA_PRED_MODE(x) (((x) & 0xff) << 16)
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#define VEPU_REG_FRAME_NUM(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_ENC_CTRL2 0x048
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#define VEPU_REG_DEBLOCKING_FILTER_MODE(x) (((x) & 0x3) << 30)
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#define VEPU_REG_H264_SLICE_SIZE(x) (((x) & 0x7f) << 23)
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#define VEPU_REG_DISABLE_QUARTER_PIXEL_MV BIT(22)
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#define VEPU_REG_H264_TRANS8X8_MODE BIT(21)
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#define VEPU_REG_CABAC_INIT_IDC(x) (((x) & 0x3) << 19)
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#define VEPU_REG_ENTROPY_CODING_MODE BIT(18)
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#define VEPU_REG_H264_INTER4X4_MODE BIT(17)
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#define VEPU_REG_H264_STREAM_MODE BIT(16)
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#define VEPU_REG_INTRA16X16_MODE(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_ENC_CTRL3 0x04c
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#define VEPU_REG_SPLIT_MV_MODE_EN BIT(30)
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#define VEPU_REG_QMV_PENALTY(x) (((x) & 0x3ff) << 20)
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#define VEPU_REG_4MV_PENALTY(x) (((x) & 0x3ff) << 10)
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#define VEPU_REG_1MV_PENALTY(x) (((x) & 0x3ff) << 0)
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#define VEPU_REG_ENC_CTRL_4 0x054
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#define VEPU_REG_SKIP_MACROBLOCK_PENALTY(x) (((x) & 0xff) << 24)
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#define VEPU_REG_COMPLETED_SLICES(x) (((x) & 0xff) << 16)
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#define VEPU_REG_INTER_MODE(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_STR_HDR_REM_MSB 0x058
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#define VEPU_REG_STR_HDR_REM_LSB 0x05c
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#define VEPU_REG_STR_BUF_LIMIT 0x060
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#define VEPU_REG_MAD_CTRL 0x064
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#define VEPU_REG_MAD_QP_ADJUSTMENT(x) (((x) & 0xf) << 28)
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#define VEPU_REG_MAD_THRESHOLD(x) (((x) & 0x3f) << 22)
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#define VEPU_REG_QP_SUM(x) (((x) & 0x001fffff) * 2)
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#define VEPU_REG_QP_VAL 0x06c
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#define VEPU_REG_H264_LUMA_INIT_QP(x) (((x) & 0x3f) << 26)
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#define VEPU_REG_H264_QP_MAX(x) (((x) & 0x3f) << 20)
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#define VEPU_REG_H264_QP_MIN(x) (((x) & 0x3f) << 14)
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#define VEPU_REG_H264_CHKPT_DISTANCE(x) (((x) & 0xfff) << 0)
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#define VEPU_REG_CHECKPOINT(i) (0x070 + ((i) * 0x4))
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#define VEPU_REG_CHECKPOINT_CHECK0(x) (((x) & 0xffff))
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#define VEPU_REG_CHECKPOINT_CHECK1(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_CHECKPOINT_RESULT(x) ((((x) >> (16 - 16 \
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* (i & 1))) & 0xffff) \
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* 32)
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#define VEPU_REG_CHKPT_WORD_ERR(i) (0x084 + ((i) * 0x4))
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#define VEPU_REG_CHKPT_WORD_ERR_CHK0(x) (((x) & 0xffff))
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#define VEPU_REG_CHKPT_WORD_ERR_CHK1(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_CHKPT_DELTA_QP 0x090
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#define VEPU_REG_CHKPT_DELTA_QP_CHK0(x) (((x) & 0x0f) << 0)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK1(x) (((x) & 0x0f) << 4)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK2(x) (((x) & 0x0f) << 8)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK3(x) (((x) & 0x0f) << 12)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK4(x) (((x) & 0x0f) << 16)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK5(x) (((x) & 0x0f) << 20)
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#define VEPU_REG_CHKPT_DELTA_QP_CHK6(x) (((x) & 0x0f) << 24)
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#define VEPU_REG_RLC_CTRL 0x094
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#define VEPU_REG_STREAM_START_OFFSET(x) (((x) & 0x3f) << 23)
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#define VEPU_REG_RLC_SUM (((x) & 0x007fffff) << 0)
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#define VEPU_REG_RLC_SUM_OUT(x) (((x) & 0x007fffff) * 4)
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#define VEPU_REG_MB_CTRL 0x098
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#define VEPU_REG_MB_CNT_SET(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_MB_CNT_OUT(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_ADDR_NEXT_PIC 0x09c
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#define VEPU_REG_STABLILIZATION_OUTPUT 0x0a0
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#define VEPU_REG_STABLE_MODE_SEL(x) (((x) & 0x3) << 30)
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#define VEPU_REG_STABLE_MIN_VALUE(x) (((x) & 0xffffff) << 0)
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#define VEPU_REG_STABLE_MOTION_SUM 0x0a4
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#define VEPU_REG_ADDR_CABAC_TBL 0x0cc
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#define VEPU_REG_ADDR_MV_OUT 0x0d0
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#define VEPU_REG_RGB2YUV_CONVERSION_COEF1 0x0d4
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#define VEPU_REG_RGB2YUV_CONVERSION_COEFB(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_RGB2YUV_CONVERSION_COEFA(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_RGB2YUV_CONVERSION_COEF2 0x0d8
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#define VEPU_REG_RGB2YUV_CONVERSION_COEFE(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_RGB2YUV_CONVERSION_COEFC(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_RGB_MASK_MSB 0x0dc
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#define VEPU_REG_RGB_MASK_B_MSB(x) (((x) & 0x1f) << 26)
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#define VEPU_REG_RGB_MASK_G_MSB(x) (((x) & 0x1f) << 21)
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#define VEPU_REG_RGB_MASK_R_MSB(x) (((x) & 0x1f) << 16)
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#define VEPU_REG_RGB2YUV_CONVERSION_COEFF(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_INTRA_AREA_CTRL 0x0e0
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#define VEPU_REG_INTRA_AREA_LEFT(x) (((x) & 0xff) << 24)
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#define VEPU_REG_INTRA_AREA_RIGHT(x) (((x) & 0xff) << 16)
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#define VEPU_REG_INTRA_AREA_TOP(x) (((x) & 0xff) << 8)
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#define VEPU_REG_INTRA_AREA_BOTTOM(x) (((x) & 0xff) << 0)
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#define VEPU_REG_CIR_INTRA_CTRL 0x0e4
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#define VEPU_REG_CIR_INTRA_FIRST_MB(x) (((x) & 0xffff) << 16)
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#define VEPU_REG_CIR_INTRA_INTERVAL(x) (((x) & 0xffff) << 0)
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#define VEPU_REG_ROI1 0x0f0
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#define VEPU_REG_ROI1_LEFT_MB(x) (((x) & 0xff) << 24)
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#define VEPU_REG_ROI1_RIGHT_MB(x) (((x) & 0xff) << 16)
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#define VEPU_REG_ROI1_TOP_MB(x) (((x) & 0xff) << 8)
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#define VEPU_REG_ROI1_BOTTOM_MB(x) (((x) & 0xff) << 0)
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#define VEPU_REG_ROI2 0x0f4
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#define VEPU_REG_ROI2_LEFT_MB(x) (((x) & 0xff) << 24)
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#define VEPU_REG_ROI2_RIGHT_MB(x) (((x) & 0xff) << 16)
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#define VEPU_REG_ROI2_TOP_MB(x) (((x) & 0xff) << 8)
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#define VEPU_REG_ROI2_BOTTOM_MB(x) (((x) & 0xff) << 0)
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#define VEPU_REG_MVC_RELATE 0x0f8
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#define VEPU_REG_ZERO_MV_FAVOR_D2(x) (((x) & 0xf) << 28)
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#define VEPU_REG_PENALTY_4X4MV(x) (((x) & 0x1ff) << 19)
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#define VEPU_REG_MVC_PRIORITY_ID(x) (((x) & 0x7) << 16)
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#define VEPU_REG_MVC_VIEW_ID(x) (((x) & 0x7) << 13)
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#define VEPU_REG_MVC_TEMPORAL_ID(x) (((x) & 0x7) << 10)
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#define VEPU_REG_MVC_ANCHOR_PIC_FLAG BIT(9)
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#define VEPU_REG_MVC_INTER_VIEW_FLAG BIT(8)
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#define VEPU_REG_ROI_QP_DELTA_1 (((x) & 0xf) << 4)
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#define VEPU_REG_ROI_QP_DELTA_2 (((x) & 0xf) << 0)
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#define VEPU_REG_DMV_PENALTY_TBL(i) (0x180 + ((i) * 0x4))
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#define VEPU_REG_DMV_PENALTY_TABLE_BIT(x, i) (x << i * 8)
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#define VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i) (0x200 + ((i) * 0x4))
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#define VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(x, i) (x << i * 8)
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#define VEPU1_H264E_NUM_REGS 164
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typedef struct H264eVpu1RegSet_t {
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RK_U32 val[VEPU1_H264E_NUM_REGS];
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} H264eVpu1RegSet;
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#endif
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