/*
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* Copyright 2016 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_vpu_h263d"
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#include <stdio.h>
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#include <string.h>
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#include "mpp_err.h"
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#include "mpp_mem.h"
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#include "mpp_debug.h"
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#include "h263d_syntax.h"
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#include "hal_h263d_api.h"
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#include "hal_h263d_vdpu2.h"
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#include "hal_h263d_vdpu2_reg.h"
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#include "hal_h263d_base.h"
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static void vpu2_h263d_setup_regs_by_syntax(hal_h263_ctx *ctx, MppSyntax syntax)
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{
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Vpu2H263dRegSet_t *regs = (Vpu2H263dRegSet_t*)ctx->regs;
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DXVA2_DecodeBufferDesc **data = syntax.data;
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DXVA_PicParams_H263 *pp = NULL;
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RK_U32 stream_length = 0;
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RK_U32 stream_used = 0;
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RK_U32 i;
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for (i = 0; i < syntax.number; i++) {
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DXVA2_DecodeBufferDesc *desc = data[i];
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switch (desc->CompressedBufferType) {
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case DXVA2_PictureParametersBufferType : {
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pp = (DXVA_PicParams_H263 *)desc->pvPVPState;
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} break;
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case DXVA2_BitStreamDateBufferType : {
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stream_length = desc->DataSize;
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stream_used = desc->DataOffset;
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} break;
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default : {
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mpp_err_f("found invalid buffer descriptor type %d\n", desc->CompressedBufferType);
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} break;
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}
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}
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mpp_assert(pp);
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mpp_assert(stream_length);
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mpp_assert(stream_used);
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regs->reg120.sw_pic_mb_width = (pp->vop_width + 15) >> 4;
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regs->reg120.sw_pic_mb_hight_p = (pp->vop_height + 15) >> 4;
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regs->reg120.sw_mb_width_off = pp->vop_width & 0xf;
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regs->reg120.sw_mb_height_off = pp->vop_height & 0xf;
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regs->reg53_dec_mode = 2;
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regs->reg50_dec_ctrl.sw_filtering_dis = 1;
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regs->reg136.sw_rounding = 0;
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regs->reg51_stream_info.sw_init_qp = pp->vop_quant;
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regs->reg122.sw_sync_markers_en = 1;
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{
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/*
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* update stream base address here according to consumed bit length
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* 1. hardware start address has to be 64 bit align
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* 2. hardware need to know which is the start bit in
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* 2. pass (10bit fd + (offset << 10)) register value to kernel
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*/
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RK_U32 val = regs->reg64_input_stream_base;
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RK_U32 consumed_bytes = stream_used >> 3;
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RK_U32 consumed_bytes_align = consumed_bytes & (~0x7);
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RK_U32 start_bit_offset = stream_used & 0x3F;
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RK_U32 left_bytes = stream_length - consumed_bytes_align;
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if (consumed_bytes_align) {
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mpp_dev_set_reg_offset(ctx->dev, 64, consumed_bytes_align);
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}
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regs->reg64_input_stream_base = val;
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regs->reg122.sw_stream_start_word = start_bit_offset;
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regs->reg51_stream_info.sw_stream_len = left_bytes;
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}
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regs->reg122.sw_vop_time_incr = pp->vop_time_increment_resolution;
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switch (pp->vop_coding_type) {
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case H263_P_VOP : {
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regs->reg57_enable_ctrl.sw_pic_inter_e = 1;
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if (ctx->fd_ref0 >= 0) {
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regs->reg131_ref0_base = (RK_U32)ctx->fd_ref0;
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regs->reg148_ref1_base = (RK_U32)ctx->fd_ref0;
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} else {
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regs->reg131_ref0_base = (RK_U32)ctx->fd_curr;
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regs->reg148_ref1_base = (RK_U32)ctx->fd_curr;
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}
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} break;
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case H263_I_VOP : {
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regs->reg57_enable_ctrl.sw_pic_inter_e = 0;
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regs->reg131_ref0_base = (RK_U32)ctx->fd_curr;
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regs->reg148_ref1_base = (RK_U32)ctx->fd_curr;
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} break;
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default : {
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/* no nothing */
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} break;
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}
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regs->reg136.sw_hrz_bit_of_fwd_mv = 1;
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regs->reg136.sw_vrz_bit_of_fwd_mv = 1;
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regs->reg136.sw_prev_pic_type = (pp->prev_coding_type == H263_P_VOP);
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}
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MPP_RET hal_vpu2_h263d_init(void *hal, MppHalCfg *cfg)
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{
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MPP_RET ret = MPP_OK;
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Vpu2H263dRegSet_t *regs = NULL;
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hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
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mpp_assert(hal);
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regs = mpp_calloc(Vpu2H263dRegSet_t, 1);
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if (NULL == regs) {
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mpp_err_f("failed to malloc register ret\n");
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ret = MPP_ERR_MALLOC;
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goto ERR_RET;
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}
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ret = mpp_dev_init(&ctx->dev, VPU_CLIENT_VDPU2);
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if (ret) {
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mpp_err_f("mpp_dev_init failed. ret: %d\n", ret);
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ret = MPP_ERR_UNKNOW;
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goto ERR_RET;
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}
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ctx->frm_slots = cfg->frame_slots;
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ctx->pkt_slots = cfg->packet_slots;
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ctx->dec_cb = cfg->dec_cb;
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ctx->regs = (void*)regs;
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return ret;
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ERR_RET:
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if (regs) {
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mpp_free(regs);
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regs = NULL;
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}
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return ret;
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}
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MPP_RET hal_vpu2_h263d_deinit(void *hal)
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{
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MPP_RET ret = MPP_OK;
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hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
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mpp_assert(hal);
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if (ctx->regs) {
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mpp_free(ctx->regs);
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ctx->regs = NULL;
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}
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if (ctx->dev) {
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mpp_dev_deinit(ctx->dev);
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ctx->dev = NULL;
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}
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return ret;
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}
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MPP_RET hal_vpu2_h263d_gen_regs(void *hal, HalTaskInfo *syn)
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{
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MPP_RET ret = MPP_OK;
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hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
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HalDecTask *task = &syn->dec;
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MppBuffer buf_frm_curr = NULL;
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MppBuffer buf_frm_ref0 = NULL;
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MppBuffer buf_pkt = NULL;
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Vpu2H263dRegSet_t *regs = (Vpu2H263dRegSet_t*)ctx->regs;
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mpp_assert(task->valid);
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mpp_assert(task->input >= 0);
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mpp_assert(task->output >= 0);
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memset(regs, 0, sizeof(Vpu2H263dRegSet_t));
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/*
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* basic register configuration setup here
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*/
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regs->reg54_endian.sw_dec_out_endian = 1;
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regs->reg54_endian.sw_dec_in_endian = 1;
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regs->reg54_endian.sw_dec_inswap32_e = 1;
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regs->reg54_endian.sw_dec_outswap32_e = 1;
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regs->reg54_endian.sw_dec_strswap32_e = 1;
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regs->reg54_endian.sw_dec_strendian_e = 1;
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regs->reg56_axi_ctrl.sw_dec_max_burst = 16;
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regs->reg52_error_concealment.sw_apf_threshold = 1;
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regs->reg57_enable_ctrl.sw_dec_timeout_e = 1;
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regs->reg57_enable_ctrl.sw_dec_clk_gate_e = 1;
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regs->reg57_enable_ctrl.sw_dec_e = 1;
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regs->reg59.sw_pred_bc_tap_0_0 = -1;
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regs->reg59.sw_pred_bc_tap_0_1 = 3;
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regs->reg59.sw_pred_bc_tap_0_2 = -6;
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regs->reg153.sw_pred_bc_tap_0_3 = 20;
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/* setup buffer for input / output / reference */
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mpp_buf_slot_get_prop(ctx->pkt_slots, task->input, SLOT_BUFFER, &buf_pkt);
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mpp_assert(buf_pkt);
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vpu_h263d_get_buffer_by_index(ctx, task->output, &buf_frm_curr);
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vpu_h263d_get_buffer_by_index(ctx, task->refer[0], &buf_frm_ref0);
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/* address registers setup first */
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ctx->fd_curr = mpp_buffer_get_fd(buf_frm_curr);
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ctx->fd_ref0 = (buf_frm_ref0) ? (mpp_buffer_get_fd(buf_frm_ref0)) : (-1);
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regs->reg63_cur_pic_base = (RK_U32)ctx->fd_curr;
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regs->reg64_input_stream_base = mpp_buffer_get_fd(buf_pkt);
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/* setup other registers, here will update packet address */
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vpu2_h263d_setup_regs_by_syntax(ctx, task->syntax);
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return ret;
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}
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MPP_RET hal_vpu2_h263d_start(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
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RK_U32 *regs = (RK_U32 *)ctx->regs;
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if (h263d_hal_debug & H263D_HAL_DBG_REG_PUT) {
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RK_U32 reg_count = (sizeof(Vpu2H263dRegSet_t) / sizeof(RK_U32));
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RK_U32 i = 0;
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for (i = 0; i < reg_count; i++)
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mpp_log("reg[%03d]: %08x\n", i, regs[i]);
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}
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do {
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MppDevRegWrCfg wr_cfg;
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MppDevRegRdCfg rd_cfg;
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wr_cfg.reg = regs;
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wr_cfg.size = sizeof(Vpu2H263dRegSet_t);
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wr_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
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if (ret) {
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mpp_err_f("set register write failed %d\n", ret);
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break;
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}
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rd_cfg.reg = regs;
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rd_cfg.size = sizeof(Vpu2H263dRegSet_t);
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rd_cfg.offset = 0;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
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if (ret) {
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mpp_err_f("set register read failed %d\n", ret);
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break;
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}
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
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if (ret) {
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mpp_err_f("send cmd failed %d\n", ret);
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break;
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}
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} while (0);
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(void)task;
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return ret;
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}
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MPP_RET hal_vpu2_h263d_wait(void *hal, HalTaskInfo *task)
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{
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MPP_RET ret = MPP_OK;
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hal_h263_ctx *ctx = (hal_h263_ctx *)hal;
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ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
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if (ret)
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mpp_err_f("poll cmd failed %d\n", ret);
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if (h263d_hal_debug & H263D_HAL_DBG_REG_GET) {
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RK_U32 *regs = (RK_U32 *)ctx->regs;
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RK_U32 reg_count = (sizeof(Vpu2H263dRegSet_t) / sizeof(RK_U32));
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RK_U32 i = 0;
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for (i = 0; i < reg_count; i++)
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mpp_log("reg[%03d]: %08x\n", i, regs[i]);
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}
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(void)task;
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return ret;
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}
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