/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H265E_VEPU541_REG_H__
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#define __HAL_H265E_VEPU541_REG_H__
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#include "rk_type.h"
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/* OSD position */
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typedef struct {
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RK_U32 lt_pos_x : 8; /* left-top */
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RK_U32 lt_pos_y : 8;
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RK_U32 rd_pos_x : 8; /* right-bottom */
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RK_U32 rd_pos_y : 8;
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} OsdPos;
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/* OSD palette */
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typedef struct {
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RK_U32 y : 8;
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RK_U32 u : 8;
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RK_U32 v : 8;
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RK_U32 alpha : 8;
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} OsdPlt;
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typedef struct {
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RK_U32 axi_brsp_cke : 7;
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RK_U32 cime_dspw_orsd : 1;
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RK_U32 reserve : 24;
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} v541_dtrns_cfg;
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typedef struct {
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RK_U32 Reserve0 : 7;
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RK_U32 cime_dspw_orsd : 1;
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RK_U32 reserve1 : 8;
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RK_U32 axi_brsp_cke : 8;
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RK_U32 reserve2 : 8;
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} v540_dtrns_cfg;
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typedef struct H265eV541RegSet_t {
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/* reg[000] */
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/* 0x0 - VERSION, swreg01 */
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struct {
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RK_U32 rkvenc_ver : 32; //default : 0x0000_0001
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} version;
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/* 0x4 - swreg02, ENC_STRT */
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struct {
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RK_U32 lkt_num : 8;
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RK_U32 rkvenc_cmd : 2;
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RK_U32 reserve : 6;
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RK_U32 enc_cke : 1;
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RK_U32 resetn_hw_en : 1;
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RK_U32 enc_done_tmvp_en : 1;
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RK_U32 Reserve : 13;
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} enc_strt;
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/* 0x8 - ENC_CLR */
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struct {
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RK_U32 safe_clr : 1;
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RK_U32 force_clr : 1;
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RK_U32 reserve : 30;
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} enc_clr;//swreg03
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/* 0xc - swreg04, LKT_ADDR */
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struct {
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RK_U32 lkt_addr : 32;
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} lkt_addr;
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/* 0x10 - swreg05, INT_EN */
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struct {
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RK_U32 enc_done_en : 1;
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RK_U32 lkt_done_en : 1;
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RK_U32 sclr_done_en : 1;
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RK_U32 slc_done_en : 1;
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RK_U32 bsf_ovflw_en : 1;
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RK_U32 brsp_ostd_en : 1;
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RK_U32 wbus_err_en : 1;
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RK_U32 rbus_err_en : 1;
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RK_U32 wdg_en : 1;
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RK_U32 reserve : 23;
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} int_en;
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struct {
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RK_U32 enc_done_msk : 1;
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RK_U32 lkt_done_msk : 1;
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RK_U32 sclr_done_msk : 1;
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RK_U32 slc_done_msk : 1;
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RK_U32 bsf_folw_msk : 1;
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RK_U32 brsp_otsd_msk : 1;
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RK_U32 wbus_err_msk : 1;
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RK_U32 rbus_err_msk : 1;
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RK_U32 wdg_msk : 1;
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RK_U32 reserved : 23;;
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} int_msk; //swreg06, INT_MSK
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struct {
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RK_U32 enc_done_clr : 1;
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RK_U32 lkt_done_clr : 1;
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RK_U32 sclr_done_clr : 1;
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RK_U32 slc_done_clr : 1;
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RK_U32 bsf_folw_clr : 1;
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RK_U32 brsp_otsd_clr : 1;
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RK_U32 wbus_err_clr : 1;
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RK_U32 rbus_err_clr : 1;
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RK_U32 wdg_msk : 1;
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RK_U32 reserved : 23;
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} int_clr; //swreg07, INT_CLR
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/* 0x1C - swreg08, INT_STA */
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struct {
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RK_U32 reserve : 32;
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} int_stus;
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RK_U32 reserved_0x20_0x2c[4];
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/* 0x30 - swreg09, ENC_RSL */
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struct {
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RK_U32 pic_wd8_m1 : 9;
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RK_U32 reserve0 : 1;
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RK_U32 pic_wfill : 6;
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RK_U32 pic_hd8_m1 : 9;
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RK_U32 reserve1 : 1;
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RK_U32 pic_hfill : 6;
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} enc_rsl;
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/* 0x34 - ENC_PIC */
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struct {
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RK_U32 enc_stnd : 1;
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RK_U32 roi_en : 1;
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RK_U32 cur_frm_ref : 1;
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RK_U32 mei_stor : 1;
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RK_U32 bs_scp : 1;
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RK_U32 rdo_wgt_sel : 1;
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RK_U32 reserved : 2;
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RK_U32 pic_qp : 6;
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RK_U32 tot_poc_num : 5;
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RK_U32 log2_ctu_num : 4;
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RK_U32 atr_thd_sel : 1;
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RK_U32 dchs_rxid : 2;
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RK_U32 dchs_txid : 2;
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RK_U32 dchs_rxe : 1;
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RK_U32 satd_byps_en : 1;
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RK_U32 slen_fifo : 1;
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RK_U32 node_int : 1;
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} enc_pic; //swreg10
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struct {
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RK_U32 vs_load_thd : 24;
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RK_U32 rfp_load_thd : 8;
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} enc_wdg; //swreg11, ENC_WDG
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/* 0x3c - DTRNS_MAP */
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struct {
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RK_U32 lpfw_bus_ordr : 1; /* vepu540 used */
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RK_U32 cmvw_bus_ordr : 1;
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RK_U32 dspw_bus_ordr : 1;
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RK_U32 rfpw_bus_ordr : 1;
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RK_U32 src_bus_edin : 4;
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RK_U32 meiw_bus_edin : 4;
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RK_U32 bsw_bus_edin : 3;
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RK_U32 lktr_bus_edin : 4;
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RK_U32 roir_bus_edin : 4;
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RK_U32 lktw_bus_edin : 4;
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RK_U32 afbc_bsize : 1;
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RK_U32 reserved : 4;
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} dtrns_map; //swreg12
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union {
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v541_dtrns_cfg dtrns_cfg_541;
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v540_dtrns_cfg dtrns_cfg_540;
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};
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/* 0x44 - SRC_FMT */
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struct {
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RK_U32 alpha_swap : 1;
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RK_U32 rbuv_swap : 1;
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RK_U32 src_cfmt : 4;
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RK_U32 src_range : 1;
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RK_U32 out_fmt_cfg : 1; //vepu540
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RK_U32 reserve : 24;
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} src_fmt;
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/* 0x48 - SRC_UDFY */
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struct {
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RK_S32 wght_b2y : 9;
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RK_S32 wght_g2y : 9;
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RK_S32 wght_r2y : 9;
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RK_S32 reserved : 5;
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} src_udfy;
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/* 0x4c - SRC_UDFU */
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struct {
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RK_S32 wght_b2u : 9;
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RK_S32 wght_g2u : 9;
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RK_S32 wght_r2u : 9;
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RK_S32 reserved : 5;
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} src_udfu;
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/* 0x50 - SRC_UDFV */
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struct {
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RK_S32 wght_b2v : 9;
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RK_S32 wght_g2v : 9;
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RK_S32 wght_r2v : 9;
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RK_S32 reserved : 5;
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} src_udfv;
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/* 0x54 - SRC_UDFO */
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struct {
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RK_U32 ofst_v : 8;
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RK_U32 ofst_u : 8;
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RK_U32 ofst_y : 5;
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RK_U32 reserve : 11;
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} src_udfo;
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/* 0x58 - SRC_PROC */
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struct {
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RK_U32 reserved0 : 26;
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RK_U32 src_mirr : 1;
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RK_U32 src_rot : 2;
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RK_U32 txa_en : 1;
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RK_U32 afbcd_en : 1;
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RK_U32 reserved1 : 1;
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} src_proc;
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/* 0x5c - MMU0_DTE_ADDR */
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struct {
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RK_U32 tile_width_m1 : 6;
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RK_U32 reserved0 : 10;
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RK_U32 tile_height_m1 : 6;
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RK_U32 reserved1 : 9;
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RK_U32 tile_en : 1;
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} tile_cfg;
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/* 0x60 - MMU1_DTE_ADDR */
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struct {
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RK_U32 tile_x : 6;
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RK_U32 reserved0 : 10;
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RK_U32 tile_y : 6;
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RK_U32 reserved1 : 10;
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} tile_pos;
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/* 0x64 - KLUT_OFST */
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struct {
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RK_U32 chrm_kult_ofst : 3;
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RK_U32 reserved : 29;
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} klut_ofst;
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/* 0x68-0xc4 - KLUT_WGT */
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struct {
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RK_U32 chrm_klut_wgt0 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt1 : 9;
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} klut_wgt0;
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struct {
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RK_U32 chrm_klut_wgt1 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt2 : 18;
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} klut_wgt1;
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struct {
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RK_U32 chrm_klut_wgt3 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt4 : 9;
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} klut_wgt2;
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struct {
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RK_U32 chrm_klut_wgt4 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt5 : 18;
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} klut_wgt3;
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struct {
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RK_U32 chrm_klut_wgt6 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt7 : 9;
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} klut_wgt4;
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struct {
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RK_U32 chrm_klut_wgt7 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt8 : 18;
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} klut_wgt5;
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struct {
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RK_U32 chrm_klut_wgt9 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt10 : 9;
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} klut_wgt6;
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struct {
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RK_U32 chrm_klut_wgt10 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt11 : 18;
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} klut_wgt7;
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struct {
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RK_U32 chrm_klut_wgt12 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt13 : 9;
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} klut_wgt8;
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struct {
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RK_U32 chrm_klut_wgt13 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt14 : 18;
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} klut_wgt9;
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struct {
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RK_U32 chrm_klut_wgt15 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt16 : 9;
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} klut_wgt10;
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struct {
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RK_U32 chrm_klut_wgt16 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt17 : 18;
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} klut_wgt11;
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struct {
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RK_U32 chrm_klut_wgt18 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt19 : 9;
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} klut_wgt12;
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struct {
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RK_U32 chrm_klut_wgt19 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt20 : 18;
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} klut_wgt13;
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struct {
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RK_U32 chrm_klut_wgt21 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt22 : 9;
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} klut_wgt14;
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struct {
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RK_U32 chrm_klut_wgt22 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt23 : 18;
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} klut_wgt15;
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struct {
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RK_U32 chrm_klut_wgt24 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt25 : 9;
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} klut_wgt16;
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struct {
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RK_U32 chrm_klut_wgt25 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt26 : 18;
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} klut_wgt17;
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struct {
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RK_U32 chrm_klut_wgt27 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt28 : 9;
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} klut_wgt18;
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struct {
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RK_U32 chrm_klut_wgt28 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt29 : 18;
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} klut_wgt19;
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struct {
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RK_U32 chrm_klut_wgt30 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt31 : 9;
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} klut_wgt20;
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struct {
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RK_U32 chrm_klut_wgt31 : 9;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt32 : 18;
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} klut_wgt21;
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struct {
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RK_U32 chrm_klut_wgt33 : 18;
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RK_U32 reserved : 5;
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RK_U32 chrm_klut_wgt34 : 9;
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} klut_wgt22;
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/* 0xc4 - klut_wgt23 */
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struct {
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RK_U32 chrm_klut_wgt34 : 9;
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RK_U32 reserved : 23;
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} klut_wgt23;
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/* 0xc8 - RC_CFG */
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struct {
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RK_U32 rc_en : 1;
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RK_U32 aqmode_en : 1;
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RK_U32 qp_mode : 1;
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RK_U32 reserved : 13;
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RK_U32 rc_ctu_num : 16;
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} rc_cfg;
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/* 0xcc - RC_QP */
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struct {
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RK_U32 reserved : 16;
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RK_U32 rc_qp_range : 4;
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RK_U32 rc_max_qp : 6;
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RK_U32 rc_min_qp : 6;
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} rc_qp;
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/* 0xd0 - swreg55, RC_TGT */
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struct {
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RK_U32 ctu_ebits : 20;
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RK_U32 reserve : 12;
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} rc_tgt;
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/* 0xd4 - RC_ADJ0 */
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struct {
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RK_S32 qp_adjust0 : 5;
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RK_S32 qp_adjust1 : 5;
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RK_S32 qp_adjust2 : 5;
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RK_S32 qp_adjust3 : 5;
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RK_S32 qp_adjust4 : 5;
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RK_S32 reserved : 7;
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} rc_adj0;
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/* 0xd8 - RCADJ1 */
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struct {
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RK_S32 qp_adjust5 : 5;
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RK_S32 qp_adjust6 : 5;
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RK_S32 qp_adjust7 : 5;
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RK_S32 qp_adjust8 : 5;
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RK_S32 reserved : 12;
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} rc_adj1;
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/* 0xdc-0xfc swreg47, */
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struct {
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RK_S32 bits_thd0;
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} rc_erp0; //RC_ERP0
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struct {
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RK_S32 bits_thd1;
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} rc_erp1; //swreg48, RC_ERP1
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struct {
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RK_S32 bits_thd2;
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} rc_erp2; //swreg49, RC_ERP2
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struct {
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RK_S32 bits_thd3;
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} rc_erp3; //swreg50, RC_ERP3
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struct {
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RK_S32 bits_thd4;
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} rc_erp4; //swreg51, RC_ERP4
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/* 0xec-0xf8 */
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struct {
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RK_S32 bits_thd5;
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} rc_erp5;
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struct {
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RK_S32 bits_thd6;
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} rc_erp6;
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struct {
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RK_S32 bits_thd7;
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} rc_erp7;
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/* 0xfc - RC_ERP8 */
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struct {
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RK_S32 bits_thd8;
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} rc_erp8;
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/* 0x100 - QPMAP0 */
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struct {
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RK_U32 qpmin_area0 : 6;
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RK_U32 qpmax_area0 : 6;
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RK_U32 qpmin_area1 : 6;
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RK_U32 qpmax_area1 : 6;
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RK_U32 qpmin_area2 : 6;
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RK_U32 reserved : 2;
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} qpmap0;
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/* 0x104 - QPMAP1 */
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struct {
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RK_U32 qpmax_area2 : 6;
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RK_U32 qpmin_area3 : 6;
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RK_U32 qpmax_area3 : 6;
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RK_U32 qpmin_area4 : 6;
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RK_U32 qpmax_area4 : 6;
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RK_U32 reserved : 2;
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} qpmap1;
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/* 0x108 - QPMAP2 */
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struct {
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RK_U32 qpmin_area5 : 6;
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RK_U32 qpmax_area5 : 6;
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RK_U32 qpmin_area6 : 6;
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RK_U32 qpmax_area6 : 6;
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RK_U32 qpmin_area7 : 6;
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RK_U32 reserved : 2;
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} qpmap2;
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/* 0x10c - QPMAP3 */
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struct {
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RK_U32 qpmax_area7 : 6;
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RK_U32 reserved : 24;
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RK_U32 qpmap_mode : 2;
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} qpmap3;
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/* 0x110 - PIC_OFST */
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struct {
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RK_U32 pic_ofst_y : 13;
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RK_U32 reserved0 : 3;
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RK_U32 pic_ofst_x : 13;
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RK_U32 reserved1 : 3;
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} pic_ofst;
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/* 0x114 - swreg23, SRC_STRID */
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struct {
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RK_U32 src_ystrid : 16;
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RK_U32 src_cstrid : 16;
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} src_strid;
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RK_U32 adr_srcy_hevc; /* 0x118 */
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RK_U32 adr_srcu_hevc;
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RK_U32 adr_srcv_hevc;
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RK_U32 roi_addr_hevc;
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RK_U32 rfpw_h_addr_hevc;
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RK_U32 rfpw_b_addr_hevc;
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RK_U32 rfpr_h_addr_hevc;
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RK_U32 rfpr_b_addr_hevc;
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RK_U32 cmvw_addr_hevc;
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RK_U32 cmvr_addr_hevc;
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RK_U32 dspw_addr_hevc;
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RK_U32 dspr_addr_hevc;
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RK_U32 meiw_addr_hevc;
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RK_U32 bsbt_addr_hevc;
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RK_U32 bsbb_addr_hevc;
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RK_U32 bsbr_addr_hevc;
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RK_U32 bsbw_addr_hevc; /* 0x158 */
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/* 0x15c - swreg41, SLI_SPL */
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struct {
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RK_U32 sli_splt : 1;
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RK_U32 sli_splt_mode : 1;
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RK_U32 sli_splt_cpst : 1;
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RK_U32 sli_max_num_m1 : 10;
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RK_U32 sli_flsh : 1;
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RK_U32 reserve : 2;
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RK_U32 sli_splt_cnum_m1 : 16;
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} sli_spl;
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/* 0x160 - swreg42, SLI_SPL_BYTE */
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struct {
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RK_U32 sli_splt_byte : 18;
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RK_U32 reserve : 14;
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} sli_spl_byte;
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/* 0x164 - swreg43, ME_RNGE */
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struct {
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RK_U32 cime_srch_h : 4;
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RK_U32 cime_srch_v : 4;
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RK_U32 rime_srch_h : 3;
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RK_U32 rime_srch_v : 3;
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RK_U32 reserved : 2;
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RK_U32 dlt_frm_num : 16;
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} me_rnge;
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/* 0x168 - swreg44, ME_CNST */
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struct {
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RK_U32 pmv_mdst_h : 8;
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RK_U32 pmv_mdst_v : 8;
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RK_U32 mv_limit : 2;
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RK_U32 mv_num : 2;
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RK_U32 colmv_store : 1;
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RK_U32 colmv_load : 1;
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RK_U32 rime_dis_en : 5; /* used for rtl debug */
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RK_U32 fme_dis_en : 5; /* used for rtl debug */
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} me_cnst;
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/* 0x16c - ME_RAM */
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struct {
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RK_U32 cime_rama_max : 11;
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RK_U32 cime_rama_h : 5;
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RK_U32 cach_l2_tag : 2;
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RK_U32 cime_linebuf_w: 8; /*only used for 540*/
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RK_U32 reserved : 6;
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} me_ram;
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/*0x170 - SYNT_REF_MARK4*/
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struct {
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RK_U32 poc_lsb_lt1 : 16;
|
RK_U32 poc_lsb_lt2 : 16;
|
} synt_ref_mark4;
|
|
/*0x174 SYNT_REF_MARK5*/
|
struct {
|
RK_U32 dlt_poc_msb_cycl1 : 16;
|
RK_U32 dlt_poc_msb_cycl2 : 16;
|
} synt_ref_mark5;
|
|
struct {
|
RK_U32 osd_ch_inv_en : 8;
|
RK_U32 osd_itype : 8;
|
RK_U32 osd_lu_inv_msk : 8;
|
RK_U32 osd_ch_inv_msk : 8;
|
} osd_inv_cfg;
|
RK_U32 lpfw_addr_hevc;
|
RK_U32 lpfr_addr_hevc;
|
RK_U32 reserved_0x184_0x190[4];
|
|
/* 0x194 - REG_THD, reserved */
|
RK_U32 reg_thd;
|
|
/* 0x198 - swreg56, RDO_CFG */
|
struct {
|
RK_U32 ltm_col : 1;
|
RK_U32 ltm_idx0l0 : 1;
|
RK_U32 chrm_special : 1;
|
RK_U32 rdoq_en : 1; /* may be used in the future */
|
RK_U32 reserved0 : 2;
|
RK_U32 cu_inter_en : 4;
|
RK_U32 reserved1 : 9;
|
RK_U32 cu_intra_en : 4;
|
RK_U32 chrm_klut_en : 1;
|
RK_U32 seq_scaling_matrix_present_flg : 2;
|
RK_U32 reserved2 : 5;
|
RK_U32 stad_byps_flg : 1; /*only for 540*/
|
} rdo_cfg;
|
|
/* 0x19c - swreg57, SYNT_NAL */
|
struct {
|
RK_U32 nal_unit_type : 6;
|
RK_U32 reserve : 26;
|
} synt_nal;
|
|
/* 0x1a0 - swreg58, SYNT_SPS */
|
struct {
|
RK_U32 smpl_adpt_ofst_en : 1;
|
RK_U32 num_st_ref_pic : 7;
|
RK_U32 lt_ref_pic_prsnt : 1;
|
RK_U32 num_lt_ref_pic : 6;
|
RK_U32 tmpl_mvp_en : 1;
|
RK_U32 log2_max_poc_lsb : 4;
|
RK_U32 strg_intra_smth : 1;
|
RK_U32 reserved : 11;
|
} synt_sps;
|
|
/* 0x1a4 - swreg59, SYNT_PPS */
|
struct {
|
RK_U32 dpdnt_sli_seg_en : 1;
|
RK_U32 out_flg_prsnt_flg : 1;
|
RK_U32 num_extr_sli_hdr : 3;
|
RK_U32 sgn_dat_hid_en : 1;
|
RK_U32 cbc_init_prsnt_flg : 1;
|
RK_U32 pic_init_qp : 6;
|
RK_U32 cu_qp_dlt_en : 1;
|
RK_U32 chrm_qp_ofst_prsn : 1;
|
RK_U32 lp_fltr_acrs_sli : 1;
|
RK_U32 dblk_fltr_ovrd_en : 1;
|
RK_U32 lst_mdfy_prsnt_flg : 1;
|
RK_U32 sli_seg_hdr_extn : 1;
|
RK_U32 cu_qp_dlt_depth : 2;
|
RK_U32 lpf_fltr_acrs_til : 1; /*only for 540*/
|
RK_U32 reserved : 10;
|
} synt_pps;
|
|
/* 0x1a8 - swreg60, SYNT_SLI0 */
|
struct {
|
RK_U32 cbc_init_flg : 1;
|
RK_U32 mvd_l1_zero_flg : 1;
|
RK_U32 merge_up_flag : 1;
|
RK_U32 merge_left_flag : 1;
|
RK_U32 reserved : 1;
|
RK_U32 ref_pic_lst_mdf_l0 : 1;
|
RK_U32 num_refidx_l1_act : 2;
|
RK_U32 num_refidx_l0_act : 2;
|
RK_U32 num_refidx_act_ovrd : 1;
|
RK_U32 sli_sao_chrm_flg : 1;
|
RK_U32 sli_sao_luma_flg : 1;
|
RK_U32 sli_tmprl_mvp_en : 1;
|
RK_U32 pic_out_flg : 1;
|
RK_U32 sli_type : 2;
|
RK_U32 sli_rsrv_flg : 7;
|
RK_U32 dpdnt_sli_seg_flg : 1;
|
RK_U32 sli_pps_id : 6;
|
RK_U32 no_out_pri_pic : 1;
|
} synt_sli0;
|
|
/* 0x1ac - swreg61, SYNT_SLI1 */
|
struct {
|
RK_S32 sli_tc_ofst_div2 : 4;
|
RK_S32 sli_beta_ofst_div2 : 4;
|
RK_U32 sli_lp_fltr_acrs_sli : 1;
|
RK_U32 sli_dblk_fltr_dis : 1;
|
RK_U32 dblk_fltr_ovrd_flg : 1;
|
RK_S32 sli_cb_qp_ofst : 5;
|
RK_U32 sli_qp : 6;
|
RK_U32 max_mrg_cnd : 3;
|
RK_U32 col_ref_idx : 1;
|
RK_U32 col_frm_l0_flg : 1;
|
RK_U32 lst_entry_l0 : 4;
|
RK_U32 reserved : 1;
|
} synt_sli1;
|
|
/* 0x1b0 - swreg62, SYNT_SLI2_RODR */
|
struct {
|
RK_U32 sli_poc_lsb : 16;
|
RK_U32 sli_hdr_ext_len : 9;
|
RK_U32 reserve : 7;
|
} synt_sli2_rodr;
|
|
/* 0x1b4 - swreg63, SYNT_REF_MARK0 */
|
struct {
|
RK_U32 st_ref_pic_flg : 1;
|
RK_U32 poc_lsb_lt0 : 16;
|
RK_U32 lt_idx_sps : 5;
|
RK_U32 num_lt_pic : 2;
|
RK_U32 st_ref_pic_idx : 6;
|
RK_U32 num_lt_sps : 2;
|
} synt_ref_mark0;
|
|
/* 0x1b8 - swreg64, SYNT_REF_MARK1 */
|
struct {
|
RK_U32 used_by_s0_flg : 4;
|
RK_U32 num_pos_pic : 1;
|
RK_U32 num_neg_pic : 5;
|
RK_U32 dlt_poc_msb_cycl0 : 16;
|
RK_U32 dlt_poc_msb_prsnt0 : 1;
|
RK_U32 dlt_poc_msb_prsnt1 : 1;
|
RK_U32 dlt_poc_msb_prsnt2 : 1;
|
RK_U32 used_by_lt_flg0 : 1;
|
RK_U32 used_by_lt_flg1 : 1;
|
RK_U32 used_by_lt_flg2 : 1;
|
} synt_ref_mark1;
|
|
RK_U32 reserved_0x1bc; /* not used for a long time */
|
|
/* 0x1c0 - OSD_CFG */
|
struct {
|
RK_U32 osd_en : 8;
|
RK_U32 osd_inv : 8;
|
RK_U32 osd_clk_sel : 1;
|
RK_U32 osd_plt_type : 1;
|
RK_U32 reserved : 14;
|
} osd_cfg;
|
|
/* 0x1c4 - OSD_INV */
|
struct {
|
RK_U32 osd_inv_r0 : 4;
|
RK_U32 osd_inv_r1 : 4;
|
RK_U32 osd_inv_r2 : 4;
|
RK_U32 osd_inv_r3 : 4;
|
RK_U32 osd_inv_r4 : 4;
|
RK_U32 osd_inv_r5 : 4;
|
RK_U32 osd_inv_r6 : 4;
|
RK_U32 osd_inv_r7 : 4;
|
} osd_inv;
|
|
/* 0x1c8 - SYNT_REF_MARK2 */
|
struct {
|
RK_U32 dlt_poc_s0_m10 : 16;
|
RK_U32 dlt_poc_s0_m11 : 16;
|
} synt_ref_mark2;
|
|
/* 0x1cc - SYNT_REF_MARK3 */
|
struct {
|
RK_U32 dlt_poc_s0_m12 : 16;
|
RK_U32 dlt_poc_s0_m13 : 16;
|
} synt_ref_mark3;
|
|
/* 0x1d0-0x1ec - OSD_POS0-OSD_POS7 */
|
OsdPos osd_pos[8];
|
|
/* 0x1f0-0x20c - OSD_ADDR0-OSD_ADDR7 */
|
RK_U32 osd_addr[8];
|
|
/* 0x210 - ST_BSL */
|
struct {
|
RK_U32 bs_lgth : 32;
|
} st_bsl;
|
|
/* 0x214 - ST_SSE_L32 */
|
struct {
|
RK_U32 sse_l32 : 32;
|
} st_sse_l32;
|
|
/* 0x218 - ST_SSE_QP */
|
struct {
|
RK_U32 qp_sum : 24; /* sum of valid CU8x8s' QP */
|
RK_U32 sse_h8 : 8;
|
} st_sse_qp;
|
|
/* 0x21c - ST_SAO */
|
struct {
|
RK_U32 slice_scnum : 12;
|
RK_U32 slice_slnum : 12;
|
RK_U32 reserve : 8;
|
} st_sao;
|
|
/* 0x220 - MMU0_STA, used by hardware?? */
|
RK_U32 mmu0_sta;
|
RK_U32 mmu1_sta;
|
|
/* 0x228 - ST_ENC */
|
struct {
|
RK_U32 st_enc : 2;
|
RK_U32 axiw_cln : 2;
|
RK_U32 axir_cln : 2;
|
RK_U32 reserve : 26;
|
} st_enc;
|
|
/* 0x22c - ST_LKT */
|
struct {
|
RK_U32 fnum_enc : 8;
|
RK_U32 fnum_cfg : 8;
|
RK_U32 fnum_int : 8;
|
RK_U32 reserve : 8;
|
} st_lkt;
|
|
/* 0x230 - ST_NOD */
|
struct {
|
RK_U32 node_addr : 32;
|
} st_nod;
|
|
/* 0x234 - ST_BSB */
|
struct {
|
RK_U32 Bsbw_ovfl : 1;
|
RK_U32 reserve : 2;
|
RK_U32 bsbw_addr : 29;
|
} st_bsb;
|
|
/* 0x238 - ST_DTRNS */
|
struct {
|
RK_U32 axib_idl : 7;
|
RK_U32 axib_ful : 7;
|
RK_U32 axib_err : 7;
|
RK_U32 axir_err : 6;
|
RK_U32 reserve : 5;
|
} st_dtrns;
|
|
/* 0x23c - ST_SNUM */
|
struct {
|
RK_U32 slice_num : 6;
|
RK_U32 reserve : 26;
|
} st_snum;
|
|
/* 0x240 - ST_SLEN */
|
struct {
|
RK_U32 slice_len : 23;
|
RK_U32 reserve : 9;
|
} st_slen;
|
|
/* 0x244-0x340 - debug registers
|
* ST_LVL64_INTER_NUM etc.
|
*/
|
RK_U32 st_lvl64_inter_num;
|
RK_U32 st_lvl32_inter_num;
|
RK_U32 st_lvl16_inter_num;
|
RK_U32 st_lvl8_inter_num;
|
RK_U32 st_lvl32_intra_num;
|
RK_U32 st_lvl16_intra_num;
|
RK_U32 st_lvl8_intra_num;
|
RK_U32 st_lvl4_intra_num;
|
RK_U32 st_cu_num_qp[52];
|
RK_U32 st_madp;
|
RK_U32 st_ctu_num; /* used for MADP calculation */
|
RK_U32 st_madi;
|
RK_U32 st_mb_num; /* used for MADI calculation */
|
|
} H265eV541RegSet;
|
|
typedef struct H265eV541IoctlExtraInfoElem_t {
|
RK_U32 reg_idx;
|
RK_U32 offset;
|
} H265eV541IoctlExtraInfoElem;
|
|
typedef struct H265eV541IoctlExtraInfo_t {
|
RK_U32 magic;
|
RK_U32 cnt;
|
H265eV541IoctlExtraInfoElem elem[20];
|
} H265eV541IoctlExtraInfo;
|
|
typedef struct H265eV541IoctlOutputElem_t {
|
RK_U32 hw_status;
|
|
struct {
|
RK_U32 bs_lgth : 32;
|
} st_bsl;
|
|
/* 0x214 - ST_SSE_L32 */
|
struct {
|
RK_U32 sse_l32 : 32;
|
} st_sse_l32;
|
|
/* 0x218 - ST_SSE_QP */
|
struct {
|
RK_U32 qp_sum : 24; /* sum of valid CU8x8s' QP */
|
RK_U32 sse_h8 : 8;
|
} st_sse_qp;
|
|
/* 0x21c - ST_SAO */
|
struct {
|
RK_U32 slice_scnum : 12;
|
RK_U32 slice_slnum : 12;
|
RK_U32 reserve : 8;
|
} st_sao;
|
|
/* 0x220 - MMU0_STA, used by hardware?? */
|
RK_U32 mmu0_sta;
|
RK_U32 mmu1_sta;
|
|
/* 0x228 - ST_ENC */
|
struct {
|
RK_U32 st_enc : 2;
|
RK_U32 axiw_cln : 2;
|
RK_U32 axir_cln : 2;
|
RK_U32 reserve : 26;
|
} st_enc;
|
|
/* 0x22c - ST_LKT */
|
struct {
|
RK_U32 fnum_enc : 8;
|
RK_U32 fnum_cfg : 8;
|
RK_U32 fnum_int : 8;
|
RK_U32 reserve : 8;
|
} st_lkt;
|
|
/* 0x230 - ST_NOD */
|
struct {
|
RK_U32 node_addr : 32;
|
} st_nod;
|
|
/* 0x234 - ST_BSB */
|
struct {
|
RK_U32 Bsbw_ovfl : 1;
|
RK_U32 reserve : 2;
|
RK_U32 bsbw_addr : 29;
|
} st_bsb;
|
|
/* 0x238 - ST_DTRNS */
|
struct {
|
RK_U32 axib_idl : 7;
|
RK_U32 axib_ful : 7;
|
RK_U32 axib_err : 7;
|
RK_U32 axir_err : 6;
|
RK_U32 reserve : 5;
|
} st_dtrns;
|
|
/* 0x23c - ST_SNUM */
|
struct {
|
RK_U32 slice_num : 6;
|
RK_U32 reserve : 26;
|
} st_snum;
|
|
/* 0x240 - ST_SLEN */
|
struct {
|
RK_U32 slice_len : 23;
|
RK_U32 reserve : 9;
|
} st_slen;
|
RK_U32 st_lvl64_inter_num;
|
RK_U32 st_lvl32_inter_num;
|
RK_U32 st_lvl16_inter_num;
|
RK_U32 st_lvl8_inter_num;
|
RK_U32 st_lvl32_intra_num;
|
RK_U32 st_lvl16_intra_num;
|
RK_U32 st_lvl8_intra_num;
|
RK_U32 st_lvl4_intra_num;
|
RK_U32 st_cu_num_qp[52];
|
RK_U32 st_madp;
|
RK_U32 st_ctu_num; /* used for MADP calculation */
|
RK_U32 st_madi;
|
RK_U32 st_mb_num; /* used for MADI calculation */
|
} H265eV541IoctlOutputElem;
|
|
#endif
|
