/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H264E_VEPU541_REG_L2_H__
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#define __HAL_H264E_VEPU541_REG_L2_H__
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#include "rk_type.h"
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/*
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* L2CFG_ADDR
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* Address offset: 0x3F0 Access type: read and write
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* Level2 configuration address
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*/
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/*
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* L2CFG_WDATA
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* Address offset: 0x3F4 Access type: read and write
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* L2 configuration write data
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*/
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/*
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* L2 configuration write data.
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*
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* Single access:
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* write address to VEPU_L2CFG_ADDR then write data to VEPU_L2CFG_WDATA.
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*
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* Burst access:
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* write the start address to VEPU_L2CFG_ADDR then write datas
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* (to VEPU_L2CFG_WDATA) consecutively.
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* Address will be auto increased after write VEPU_L2CFG_WDATA,
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* no need to configure VEPU_L2CFG_ADDR.
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*/
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/*
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* L2CFG_RDATA
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* Address offset: 0x3F8 Access type: read and write
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* L2 configuration read data
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*/
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struct {
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/*
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* L2 configuration read data.
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*
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* Single access:
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* write address to VEPU_L2CFG_ADDR then read data from VEPU_L2CFG_RDATA.
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*
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* Burst access:
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* write the start address to VEPU_L2CFG_ADDR then read datas
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* (from VEPU_L2CFG_RDATA) consecutively.
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* Address will be auto increased after read VEPU_L2CFG_RDATA,
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* no need to configure VEPU_L2CFG_ADDR.
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*/
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RK_U32 l2cfg_rdata;
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} reg254;
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/* reg gap 255 */
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RK_U32 reg_255;
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typedef struct Vepu541H264eRegL2Set_t {
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/*
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* IPRD_TTHDY4_0_H264 ~ IPRD_TTHDY4_1_H264
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* Address: 0x0004~0x0008 Access type: read and write
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* The texture thredsholds for H.264 LUMA 4x4 intra prediction
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*/
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RK_U16 iprd_tthdy4[4];
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/*
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* IPRD_TTHDC8_0_H264 ~ IPRD_TTHDC8_1_H264
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* Address: 0x000C~0x0010 Access type: read and write
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* The texture threshold for H.264 CHROMA 8x8 intra prediction.
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*/
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RK_U16 iprd_tthdc8[4];
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/*
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* IPRD_TTHDY8_0_H264 ~ IPRD_TTHDY8_1_H264
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* Address: 0x0014~0x0018 Access type: read and write
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* The texture thredsholds for H.264 LUMA 8x8 intra prediction
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*/
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RK_U16 iprd_tthdy8[4];
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/*
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* IPRD_TTHD_UL_H264
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* Address: 0x001C Access type: read and write
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* Texture thredsholds of up and left MB for H.264 LUMA intra prediction.
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*/
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RK_U32 iprd_tthd_ul;
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/*
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* IPRD_WGTY8_H264
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* Address: 0x0020 Access type: read and write
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* Weights of the cost for H.264 LUMA 8x8 intra prediction
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*/
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RK_U8 iprd_wgty8[4];
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/*
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* IPRD_WGTY4_H264
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* Address: 0x0024 Access type: read and write
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* Weights of the cost for H.264 LUMA 4x4 intra prediction
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*/
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RK_U8 iprd_wgty4[4];
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/*
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* IPRD_WGTY16_H264
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* Address: 0x0028 Access type: read and write
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* Weights of the cost for H.264 LUMA 16x16 intra prediction
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*/
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RK_U8 iprd_wgty16[4];
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/*
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* IPRD_WGTC8_H264
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* Address: 0x002C Access type: read and write
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* Weights of the cost for H.264 CHROMA 8x8 intra prediction
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*/
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RK_U8 iprd_wgtc8[4];
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/*
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* QNT_BIAS_COMB
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* Address: 0x0030 Access type: read and write
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* Quantization bias for H.264 and HEVC.
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*/
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struct {
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/* Quantization bias for HEVC and H.264 I frame. */
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RK_U32 qnt_bias_i : 10;
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/* Quantization bias for HEVC and H.264 P frame. */
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RK_U32 qnt_bias_p : 10;
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RK_U32 reserved : 12;
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} qnt_bias_comb;
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/*
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* ATR_THD0_H264
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* Address: 0x0034 Access type: read and write
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* H.264 anti ringing noise threshold configuration0.
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*/
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struct {
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/* The 1st threshold for H.264 anti-ringing-noise. */
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RK_U32 atr_thd0 : 12;
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RK_U32 reserved0 : 4;
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/* The 2nd threshold for H.264 anti-ringing-noise. */
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RK_U32 atr_thd1 : 12;
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RK_U32 reserved1 : 4;
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} atr_thd0_h264;
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/*
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* ATR_THD1_H264
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* Address: 0x0038 Access type: read and write
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* H.264 anti ringing noise threshold configuration1.
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*/
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struct {
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/* The 3rd threshold for H.264 anti-ringing-noise. */
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RK_U32 atr_thd2 : 12;
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RK_U32 reserved0 : 4;
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/* QP threshold of P frame for H.264 anti-ringing-nois. */
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RK_U32 atr_qp : 6;
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RK_U32 reserved1 : 10;
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} atr_thd1_h264;
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/*
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* ATR_WGT16_H264
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* Address: 0x003C Access type: read and write
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* Weights of 16x16 cost for H.264 anti ringing noise.
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*/
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struct {
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/* The 1st weight for H.264 16x16 anti-ringing-noise. */
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RK_U32 atr_lv16_wgt0 : 8;
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/* The 2nd weight for H.264 16x16 anti-ringing-noise. */
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RK_U32 atr_lv16_wgt1 : 8;
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/* The 3rd weight for H.264 16x16 anti-ringing-noise. */
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RK_U32 atr_lv16_wgt2 : 8;
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RK_U32 reserved : 8;
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} atr_wgt16_h264;
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/*
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* ATR_WGT8_H264
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* Address: 0x0040 Access type: read and write
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* Weights of 8x8 cost for H.264 anti ringing noise.
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*/
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struct {
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/* The 1st weight for H.264 8x8 anti-ringing-noise. */
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RK_U32 atr_lv8_wgt0 : 8;
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/* The 2nd weight for H.264 8x8 anti-ringing-noise. */
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RK_U32 atr_lv8_wgt1 : 8;
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/* The 3rd weight for H.264 8x8 anti-ringing-noise. */
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RK_U32 atr_lv8_wgt2 : 8;
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RK_U32 reserved : 8;
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} atr_wgt8_h264;
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/*
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* ATR_WGT4_H264
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* Address: 0x0044 Access type: read and write
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* Weights of 4x4 cost for H.264 anti ringing noise.
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*/
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struct {
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/* The 1st weight for H.264 4x4 anti-ringing-noise. */
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RK_U32 atr_lv4_wgt0 : 8;
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/* The 2nd weight for H.264 4x4 anti-ringing-noise. */
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RK_U32 atr_lv4_wgt1 : 8;
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/* The 3rd weight for H.264 4x4 anti-ringing-noise. */
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RK_U32 atr_lv4_wgt2 : 8;
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RK_U32 reserved : 8;
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} atr_wgt4_h264;
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/*
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* ATF_TTHD0_H264 ~ ATF_TTHD1_H264
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* Address: 0x0048~0x004C Access type: read and write
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* Texture threshold configuration for H.264 anti-flicker
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*/
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RK_U16 atf_tthd[4];
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/*
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* ATF_STHD0_H264
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* Address: 0x0050 Access type: read and write
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* (CME) SAD threshold configuration1 for H.264 anti-flicker.
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*/
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struct {
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/* (CME) SAD threshold0 of texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_sthd_10 : 14;
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RK_U32 reserved0 : 2;
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/* Max (CME) SAD threshold for H.264 anti-flicker. */
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RK_U32 atf_sthd_max : 14;
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RK_U32 reserved1 : 2;
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} atf_sthd0_h264;
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/*
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* ATF_STHD1_H264
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* Address: 0x0054 Access type: read and write
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* (CME) SAD threshold configuration1 for H.264 anti-flicker.
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*/
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struct {
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/* (CME) SAD threshold1 of texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_sthd_11 : 14;
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RK_U32 reserved0 : 2;
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/* (CME) SAD threshold0 of texture interval2 for H.264 anti-flicker. */
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RK_U32 atf_sthd_20 : 14;
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RK_U32 reserved1 : 2;
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} atf_sthd1_h264;
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/*
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* ATF_WGT0_H264
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* Address: 0x0058 Access type: read and write
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* Weight configuration0 for H.264 anti-flicker.
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*/
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struct {
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/* The 1st weight in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_wgt10 : 9;
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RK_U32 reserved0 : 7;
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/* The 2nd weight in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_wgt11 : 9;
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RK_U32 reserved1 : 7;
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} atf_wgt0_h264;
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/*
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* ATF_WGT1_H264
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* Address: 0x005C Access type: read and write
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* Weight configuration1 for H.264 anti-flicker.
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*/
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struct {
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/* The 3rd weight in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_wgt12 : 9;
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RK_U32 reserved0 : 7;
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/* The 1st weight in texture interval2 for H.264 anti-flicker. */
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RK_U32 atf_wgt20 : 9;
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RK_U32 reserved1 : 7;
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} atf_wgt1_h264;
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/*
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* ATF_WGT2_H264
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* Address: 0x0060 Access type: read and write
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* Weight configuration2 for H.264 anti-flicker.
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*/
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struct {
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/* The 2nd weight in texture interval2 for H.264 anti-flicker. */
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RK_U32 atf_wgt21 : 9;
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RK_U32 reserved0 : 7;
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/* The weight in texture interval3 for H.264 anti-flicker. */
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RK_U32 atf_wgt30 : 9;
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RK_U32 reserved1 : 7;
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} atf_wgt2_h264;
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/*
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* ATF_OFST0_H264
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* Address: 0x0064 Access type: read and write
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* Offset configuration0 for H.264 anti-flicker.
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*/
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struct {
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/* The 1st offset in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_ofst10 : 14;
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RK_U32 reserved0 : 2;
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/* The 2nd offset in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_ofst11 : 14;
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RK_U32 reserved1 : 2;
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} atf_ofst0_h264;
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/*
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* ATF_OFST1_H264
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* Address: 0x0068 Access type: read and write
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* Offset configuration1 for H.264 anti-flicker.
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*/
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struct {
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/* The 3rd offset in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_ofst12 : 14;
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RK_U32 reserved0 : 2;
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/* The 1st offset in texture interval2 for H.264 anti-flicker. */
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RK_U32 atf_ofst20 : 14;
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RK_U32 reserved1 : 2;
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} atf_ofst1_h264;
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/*
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* ATF_OFST2_H264
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* Address: 0x006C Access type: read and write
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* Offset configuration2 for H.264 anti-flicker.
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*/
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struct {
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/* The 2nd offset in texture interval1 for H.264 anti-flicker. */
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RK_U32 atf_ofst21 : 14;
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RK_U32 reserved0 : 2;
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/* The offset in texture interval3 for H.264 anti-flicker. */
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RK_U32 atf_ofst30 : 14;
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RK_U32 reserved1 : 2;
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} atf_ofst2_h264;
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/*
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* IPRD_WGT_QP0_HEVC ~ IPRD_WGT_QP51_HEVC
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* Address: 0x0070 ~ 0x013C Access type: read and write
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* Weight of SATD cost when QP is 0~51 for HEVC intra prediction.
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*/
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RK_U32 iprd_wgt_qp[52];
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/*
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* RDO_WGTA_QP0_COMB ~ RDO_WGTA_QP51_COMB
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* Address: 0x0140 ~ 0x020C Access type: read and write
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* Weight of group A for HEVC and H.264 RDO mode decision when QP is 0~51.
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*/
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RK_U32 wgt_qp_grpa[52];
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/*
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* RDO_WGTB_QP0_COMB ~ RDO_WGTB_QP51_COMB
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* Address: 0x0210 ~ 0x02DC Access type: read and write
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* Weight of group B for HEVC and H.264 RDO mode decision when QP is 0~51.
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*/
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RK_U32 wgt_qp_grpb[52];
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/*
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* MADI_CFG
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* Address: 0x02E0 Access type: read and write
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* MADI configuration for CU32 and CU64.
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*/
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/*
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* MADI generation mode for CU32 and CU64.
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* 1'h0: Follow 32x32 and 64x64 MADI functions.
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* 1'h1: Calculated by the mean of corresponding CU16 MADIs.
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*/
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RK_U32 madi_mode;
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/*
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* AQ_TTHD0 ~ AQ_TTHD3
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* Address: 0x02E4 ~ 0x02F0 Access type: read and write
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* Texture threshold configuration for adaptive QP adjustment.
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*/
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/* Texture threshold for adaptive QP adjustment. */
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RK_U8 aq_tthd[16];
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/*
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* AQ_STP0 ~ AQ_STP3
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* Address: 0x02F4 ~ 0x300 Access type: read and write
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* Adjustment step configuration0 for adaptive QP adjustment.
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*/
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/*
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* MADI generation mode for CU32 and CU64.
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* 1'h0: Follow 32x32 and 64x64 MADI functions.
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* 1'h1: Calculated by the mean of corresponding CU16 MADIs.
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*/
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/* QP adjust step when current texture strength is between n-1 and n step. */
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RK_S8 aq_step[16];
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/*
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* RME_MVD_PNSH_H264
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* Address: 0x0304 Access type: read and write
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* RME MVD(motion vector difference) cost penalty, H.264 only.
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*/
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struct {
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/* MVD cost penalty enable. */
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RK_U32 mvd_pnlt_e : 1;
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/* MVD cost penalty coefficienc. */
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RK_U32 mvd_pnlt_coef : 5;
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/* MVD cost penalty constant. */
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RK_U32 mvd_pnlt_cnst : 14;
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/* Low threshold of the MVs which should be punished. */
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RK_U32 mvd_pnlt_lthd : 4;
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/* High threshold of the MVs which should be punished. */
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RK_U32 mvd_pnlt_hthd : 4;
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RK_U32 reserved : 4;
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} rme_mvd_penalty;
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/*
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* ATR1_THD0_H264
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* Address: 0x0308 Access type: read and write
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* H.264 anti ringing noise threshold configuration0 of group1.
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*/
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struct {
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/* The 1st threshold for H.264 anti-ringing-noise of group1. */
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RK_U32 atr1_thd0 : 12;
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RK_U32 reserved0 : 4;
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/* The 2nd threshold for H.264 anti-ringing-noise of group1. */
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RK_U32 atr1_thd1 : 12;
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RK_U32 reserved1 : 4;
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} atr1_thd0_h264;
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/*
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* ATR1_THD0_H264
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* Address: 0x030C Access type: read and write
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* H.264 anti ringing noise threshold configuration1 of group1.
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*/
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struct {
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/* The 3rd threshold for H.264 anti-ringing-noise of group1. */
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RK_U32 atr1_thd2 : 12;
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RK_U32 reserved0 : 20;
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} atr1_thd1_h264;
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} Vepu541H264eRegL2Set;
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#endif /* __HAL_H264E_VEPU541_REG_L2_H__ */
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