/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef __HAL_H265D_CTX_H__
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#define __HAL_H265D_CTX_H__
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#include "mpp_device.h"
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#include "mpp_hal.h"
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#include "hal_bufs.h"
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#include "vdpu34x_com.h"
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#define MAX_GEN_REG 3
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typedef struct H265dRegBuf_t {
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RK_S32 use_flag;
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MppBuffer scaling_list_data;
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MppBuffer pps_data;
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MppBuffer rps_data;
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void* hw_regs;
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} H265dRegBuf;
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typedef struct HalH265dCtx_t {
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/* for hal api call back */
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const MppHalApi *api;
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/* for hardware info */
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MppClientType client_type;
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RK_U32 hw_id;
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MppDev dev;
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/* for resource */
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MppBufSlots slots;
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MppBufSlots packet_slots;
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MppBufferGroup group;
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MppBuffer cabac_table_data;
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MppBuffer scaling_list_data;
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MppBuffer pps_data;
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MppBuffer rps_data;
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RK_S32 width;
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RK_S32 height;
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RK_S32 rcb_buf_size;
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Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
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MppBuffer rcb_buf[MAX_GEN_REG];
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void* hw_regs;
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H265dRegBuf g_buf[MAX_GEN_REG];
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RK_U32 fast_mode;
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MppCbCtx *dec_cb;
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RK_U32 fast_mode_err_found;
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void *scaling_rk;
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void *scaling_qm;
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HalBufs cmv_bufs;
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RK_U32 mv_size;
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RK_S32 mv_count;
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RK_U32 is_v345;
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RK_U32 is_v34x;
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/* rcb info */
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RK_U32 chroma_fmt_idc;
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RK_U8 ctu_size;
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RK_U8 num_row_tiles;
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RK_U8 bit_depth;
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RK_U8 error_index;
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/* for vdpu34x */
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MppBuffer bufs;
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RK_S32 bufs_fd;
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RK_U32 offset_cabac;
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RK_U32 offset_spspps[MAX_GEN_REG];
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RK_U32 offset_rps[MAX_GEN_REG];
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RK_U32 offset_sclst[MAX_GEN_REG];
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RK_U32 spspps_offset;
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RK_U32 rps_offset;
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RK_U32 sclst_offset;
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void *pps_buf;
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void *sw_rps_buf;
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} HalH265dCtx;
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typedef struct ScalingList {
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/* This is a little wasteful, since sizeID 0 only needs 8 coeffs,
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* and size ID 3 only has 2 arrays, not 6. */
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RK_U8 sl[4][6][64];
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RK_U8 sl_dc[2][6];
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} scalingList_t;
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typedef struct ScalingFactor_Model {
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RK_U8 scalingfactor0[1248];
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RK_U8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
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RK_U8 scalingdc[12]; /*N1005 Vienna Meeting*/
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RK_U8 reserverd[4]; /*16Bytes align*/
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} scalingFactor_t;
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#endif
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