/*
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* (C) Copyright 2009 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX5_IMX_REGS_H__
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#define __ASM_ARCH_MX5_IMX_REGS_H__
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#define ARCH_MXC
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#if defined(CONFIG_MX51)
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#define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */
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#define IPU_SOC_BASE_ADDR 0x40000000
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#define IPU_SOC_OFFSET 0x1E000000
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#define SPBA0_BASE_ADDR 0x70000000
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#define AIPS1_BASE_ADDR 0x73F00000
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#define AIPS2_BASE_ADDR 0x83F00000
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#define CSD0_BASE_ADDR 0x90000000
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#define CSD1_BASE_ADDR 0xA0000000
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#define NFC_BASE_ADDR_AXI 0xCFFF0000
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#define CS1_BASE_ADDR 0xB8000000
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#elif defined(CONFIG_MX53)
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#define IPU_SOC_BASE_ADDR 0x18000000
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#define IPU_SOC_OFFSET 0x06000000
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#define SPBA0_BASE_ADDR 0x50000000
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#define AIPS1_BASE_ADDR 0x53F00000
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#define AIPS2_BASE_ADDR 0x63F00000
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#define CSD0_BASE_ADDR 0x70000000
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#define CSD1_BASE_ADDR 0xB0000000
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#define NFC_BASE_ADDR_AXI 0xF7FF0000
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#define IRAM_BASE_ADDR 0xF8000000
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#define CS1_BASE_ADDR 0xF4000000
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#define SATA_BASE_ADDR 0x10000000
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#else
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#error "CPU_TYPE not defined"
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#endif
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#define IRAM_SIZE 0x00020000 /* 128 KB */
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/*
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* SPBA global module enabled #0
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*/
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#define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000)
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#define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000)
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#define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000)
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#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000)
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#define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000)
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#define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000)
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#define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000)
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#define SPDIF_BASE_ADDR (SPBA0_BASE_ADDR + 0x00028000)
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#define ATA_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00030000)
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#define SLIM_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00034000)
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#define HSI2C_DMA_BASE_ADDR (SPBA0_BASE_ADDR + 0x00038000)
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#define SPBA_CTRL_BASE_ADDR (SPBA0_BASE_ADDR + 0x0003C000)
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/*
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* AIPS 1
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*/
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#define OTG_BASE_ADDR (AIPS1_BASE_ADDR + 0x00080000)
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#define GPIO1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00084000)
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#define GPIO2_BASE_ADDR (AIPS1_BASE_ADDR + 0x00088000)
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#define GPIO3_BASE_ADDR (AIPS1_BASE_ADDR + 0x0008C000)
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#define GPIO4_BASE_ADDR (AIPS1_BASE_ADDR + 0x00090000)
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#define KPP_BASE_ADDR (AIPS1_BASE_ADDR + 0x00094000)
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#define WDOG1_BASE_ADDR (AIPS1_BASE_ADDR + 0x00098000)
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#define WDOG2_BASE_ADDR (AIPS1_BASE_ADDR + 0x0009C000)
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#define GPT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A0000)
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#define SRTC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A4000)
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#define IOMUXC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000A8000)
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#define EPIT1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000AC000)
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#define EPIT2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B0000)
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#define PWM1_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B4000)
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#define PWM2_BASE_ADDR (AIPS1_BASE_ADDR + 0x000B8000)
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#define UART1_BASE (AIPS1_BASE_ADDR + 0x000BC000)
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#define UART2_BASE (AIPS1_BASE_ADDR + 0x000C0000)
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#define SRC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D0000)
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#define CCM_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D4000)
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#define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000)
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#if defined(CONFIG_MX53)
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#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000)
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#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000)
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#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000)
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#define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000)
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#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000)
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#endif
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/*
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* AIPS 2
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*/
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#define PLL1_BASE_ADDR (AIPS2_BASE_ADDR + 0x00080000)
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#define PLL2_BASE_ADDR (AIPS2_BASE_ADDR + 0x00084000)
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#define PLL3_BASE_ADDR (AIPS2_BASE_ADDR + 0x00088000)
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#ifdef CONFIG_MX53
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#define PLL4_BASE_ADDR (AIPS2_BASE_ADDR + 0x0008c000)
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#endif
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#define AHBMAX_BASE_ADDR (AIPS2_BASE_ADDR + 0x00094000)
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#define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000)
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#define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000)
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#define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000)
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#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000)
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#define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000)
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#define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000)
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#define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000)
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#define SCC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B4000)
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#define ROMCP_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B8000)
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#define RTIC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000BC000)
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#define CSPI3_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C0000)
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#define I2C2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C4000)
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#define I2C1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000C8000)
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#define SSI1_BASE_ADDR (AIPS2_BASE_ADDR + 0x000CC000)
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#define AUDMUX_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D0000)
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#define M4IF_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D8000)
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#define ESDCTL_BASE_ADDR (AIPS2_BASE_ADDR + 0x000D9000)
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#define WEIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DA000)
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#define NFC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DB000)
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#define EMI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DBF00)
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#define MIPI_HSC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000DC000)
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#define ATA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E0000)
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#define SIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000E4000)
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#define SSI3BASE_ADDR (AIPS2_BASE_ADDR + 0x000E8000)
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#define FEC_BASE_ADDR (AIPS2_BASE_ADDR + 0x000EC000)
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#define TVE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F0000)
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#define VPU_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F4000)
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#define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000)
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#if defined(CONFIG_MX53)
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#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000)
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#endif
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/*
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* WEIM CSnGCR1
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*/
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#define CSEN 1
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#define SWR (1 << 1)
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#define SRD (1 << 2)
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#define MUM (1 << 3)
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#define WFL (1 << 4)
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#define RFL (1 << 5)
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#define CRE (1 << 6)
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#define CREP (1 << 7)
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#define BL(x) (((x) & 0x7) << 8)
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#define WC (1 << 11)
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#define BCD(x) (((x) & 0x3) << 12)
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#define BCS(x) (((x) & 0x3) << 14)
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#define DSZ(x) (((x) & 0x7) << 16)
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#define SP (1 << 19)
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#define CSREC(x) (((x) & 0x7) << 20)
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#define AUS (1 << 23)
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#define GBC(x) (((x) & 0x7) << 24)
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#define WP (1 << 27)
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#define PSZ(x) (((x) & 0x0f << 28)
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/*
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* WEIM CSnGCR2
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*/
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#define ADH(x) (((x) & 0x3))
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#define DAPS(x) (((x) & 0x0f << 4)
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#define DAE (1 << 8)
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#define DAP (1 << 9)
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#define MUX16_BYP (1 << 12)
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/*
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* WEIM CSnRCR1
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*/
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#define RCSN(x) (((x) & 0x7))
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#define RCSA(x) (((x) & 0x7) << 4)
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#define OEN(x) (((x) & 0x7) << 8)
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#define OEA(x) (((x) & 0x7) << 12)
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#define RADVN(x) (((x) & 0x7) << 16)
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#define RAL (1 << 19)
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#define RADVA(x) (((x) & 0x7) << 20)
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#define RWSC(x) (((x) & 0x3f) << 24)
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/*
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* WEIM CSnRCR2
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*/
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#define RBEN(x) (((x) & 0x7))
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#define RBE (1 << 3)
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#define RBEA(x) (((x) & 0x7) << 4)
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#define RL(x) (((x) & 0x3) << 8)
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#define PAT(x) (((x) & 0x7) << 12)
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#define APR (1 << 15)
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/*
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* WEIM CSnWCR1
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*/
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#define WCSN(x) (((x) & 0x7))
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#define WCSA(x) (((x) & 0x7) << 3)
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#define WEN(x) (((x) & 0x7) << 6)
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#define WEA(x) (((x) & 0x7) << 9)
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#define WBEN(x) (((x) & 0x7) << 12)
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#define WBEA(x) (((x) & 0x7) << 15)
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#define WADVN(x) (((x) & 0x7) << 18)
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#define WADVA(x) (((x) & 0x7) << 21)
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#define WWSC(x) (((x) & 0x3f) << 24)
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#define WBED1 (1 << 30)
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#define WAL (1 << 31)
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/*
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* WEIM CSnWCR2
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*/
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#define WBED 1
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/*
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* CSPI register definitions
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*/
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#define MXC_ECSPI
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_MODE_MASK (0xf << 4)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
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#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
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#define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
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#define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
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#define MXC_CSPICTRL_MAXBITS 0xfff
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#define MXC_CSPICTRL_TC (1 << 7)
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#define MXC_CSPICTRL_RXOVF (1 << 6)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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#define MAX_SPI_BYTES 32
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/* Bit position inside CTRL register to be associated with SS */
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#define MXC_CSPICTRL_CHAN 18
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/* Bit position inside CON register to be associated with SS */
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#define MXC_CSPICON_PHA 0 /* SCLK phase control */
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#define MXC_CSPICON_POL 4 /* SCLK polarity */
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#define MXC_CSPICON_SSPOL 12 /* SS polarity */
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#define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
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#define MXC_SPI_BASE_ADDRESSES \
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CSPI1_BASE_ADDR, \
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CSPI2_BASE_ADDR, \
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CSPI3_BASE_ADDR,
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/*
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* Number of GPIO pins per port
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*/
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#define GPIO_NUM_PIN 32
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#define IIM_SREV 0x24
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#define ROM_SI_REV 0x48
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#define NFC_BUF_SIZE 0x1000
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/* M4IF */
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#define M4IF_FBPM0 0x40
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#define M4IF_FIDBP 0x48
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#define M4IF_GENP_WEIM_MM_MASK 0x00000001
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#define WEIM_GCR2_MUX16_BYP_GRANT_MASK 0x00001000
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/* Assuming 24MHz input clock with doubler ON */
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/* MFI PDF */
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#define DP_OP_864 ((8 << 4) + ((1 - 1) << 0))
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#define DP_MFD_864 (180 - 1) /* PL Dither mode */
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#define DP_MFN_864 180
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#define DP_MFN_800_DIT 60 /* PL Dither mode */
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#define DP_OP_850 ((8 << 4) + ((1 - 1) << 0))
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#define DP_MFD_850 (48 - 1)
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#define DP_MFN_850 41
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#define DP_OP_800 ((8 << 4) + ((1 - 1) << 0))
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#define DP_MFD_800 (3 - 1)
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#define DP_MFN_800 1
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#define DP_OP_700 ((7 << 4) + ((1 - 1) << 0))
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#define DP_MFD_700 (24 - 1)
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#define DP_MFN_700 7
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#define DP_OP_665 ((6 << 4) + ((1 - 1) << 0))
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#define DP_MFD_665 (96 - 1)
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#define DP_MFN_665 89
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#define DP_OP_532 ((5 << 4) + ((1 - 1) << 0))
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#define DP_MFD_532 (24 - 1)
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#define DP_MFN_532 13
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#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0))
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#define DP_MFD_400 (3 - 1)
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#define DP_MFN_400 1
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#define DP_OP_455 ((9 << 4) + ((2 - 1) << 0))
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#define DP_MFD_455 (48 - 1)
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#define DP_MFN_455 23
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#define DP_OP_216 ((6 << 4) + ((3 - 1) << 0))
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#define DP_MFD_216 (4 - 1)
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#define DP_MFN_216 3
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#define IMX_IIM_BASE (IIM_BASE_ADDR)
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#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
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#include <asm/types.h>
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#define __REG(x) (*((volatile u32 *)(x)))
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#define __REG16(x) (*((volatile u16 *)(x)))
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#define __REG8(x) (*((volatile u8 *)(x)))
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struct clkctl {
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u32 ccr;
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u32 ccdr;
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u32 csr;
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u32 ccsr;
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u32 cacrr;
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u32 cbcdr;
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u32 cbcmr;
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u32 cscmr1;
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u32 cscmr2;
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u32 cscdr1;
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u32 cs1cdr;
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u32 cs2cdr;
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u32 cdcdr;
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u32 chsccdr;
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u32 cscdr2;
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u32 cscdr3;
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u32 cscdr4;
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u32 cwdr;
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u32 cdhipr;
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u32 cdcr;
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u32 ctor;
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u32 clpcr;
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u32 cisr;
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u32 cimr;
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u32 ccosr;
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u32 cgpr;
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u32 ccgr0;
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u32 ccgr1;
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u32 ccgr2;
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u32 ccgr3;
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u32 ccgr4;
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u32 ccgr5;
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u32 ccgr6;
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#if defined(CONFIG_MX53)
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u32 ccgr7;
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#endif
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u32 cmeor;
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};
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/* DPLL registers */
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struct dpll {
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u32 dp_ctl;
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u32 dp_config;
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u32 dp_op;
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u32 dp_mfd;
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u32 dp_mfn;
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u32 dp_mfn_minus;
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u32 dp_mfn_plus;
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u32 dp_hfs_op;
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u32 dp_hfs_mfd;
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u32 dp_hfs_mfn;
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u32 dp_mfn_togc;
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u32 dp_destat;
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};
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/* WEIM registers */
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struct weim {
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u32 cs0gcr1;
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u32 cs0gcr2;
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u32 cs0rcr1;
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u32 cs0rcr2;
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u32 cs0wcr1;
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u32 cs0wcr2;
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u32 cs1gcr1;
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u32 cs1gcr2;
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u32 cs1rcr1;
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u32 cs1rcr2;
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u32 cs1wcr1;
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u32 cs1wcr2;
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u32 cs2gcr1;
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u32 cs2gcr2;
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u32 cs2rcr1;
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u32 cs2rcr2;
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u32 cs2wcr1;
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u32 cs2wcr2;
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u32 cs3gcr1;
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u32 cs3gcr2;
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u32 cs3rcr1;
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u32 cs3rcr2;
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u32 cs3wcr1;
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u32 cs3wcr2;
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u32 cs4gcr1;
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u32 cs4gcr2;
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u32 cs4rcr1;
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u32 cs4rcr2;
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u32 cs4wcr1;
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u32 cs4wcr2;
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u32 cs5gcr1;
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u32 cs5gcr2;
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u32 cs5rcr1;
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u32 cs5rcr2;
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u32 cs5wcr1;
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u32 cs5wcr2;
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u32 wcr;
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u32 wiar;
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u32 ear;
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};
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#if defined(CONFIG_MX51)
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struct iomuxc {
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u32 gpr[2];
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u32 omux0;
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u32 omux1;
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u32 omux2;
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u32 omux3;
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u32 omux4;
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};
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#elif defined(CONFIG_MX53)
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struct iomuxc {
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u32 gpr[3];
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u32 omux0;
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u32 omux1;
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u32 omux2;
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u32 omux3;
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u32 omux4;
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};
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#endif
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/* System Reset Controller (SRC) */
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struct src {
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u32 scr;
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u32 sbmr;
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u32 srsr;
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u32 reserved1[2];
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u32 sisr;
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u32 simr;
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};
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struct srtc_regs {
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u32 lpscmr; /* 0x00 */
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u32 lpsclr; /* 0x04 */
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u32 lpsar; /* 0x08 */
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u32 lpsmcr; /* 0x0c */
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u32 lpcr; /* 0x10 */
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u32 lpsr; /* 0x14 */
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u32 lppdr; /* 0x18 */
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u32 lpgr; /* 0x1c */
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u32 hpcmr; /* 0x20 */
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u32 hpclr; /* 0x24 */
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u32 hpamr; /* 0x28 */
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u32 hpalr; /* 0x2c */
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u32 hpcr; /* 0x30 */
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u32 hpisr; /* 0x34 */
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u32 hpienr; /* 0x38 */
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};
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/* CSPI registers */
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struct cspi_regs {
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u32 rxdata;
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u32 txdata;
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u32 ctrl;
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u32 cfg;
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u32 intr;
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u32 dma;
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u32 stat;
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u32 period;
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};
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struct iim_regs {
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u32 stat;
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u32 statm;
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u32 err;
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u32 emask;
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u32 fctl;
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u32 ua;
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u32 la;
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u32 sdat;
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u32 prev;
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u32 srev;
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u32 prg_p;
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u32 scs0;
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u32 scs1;
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u32 scs2;
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u32 scs3;
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u32 res0[0x1f1];
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struct fuse_bank {
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u32 fuse_regs[0x20];
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u32 fuse_rsvd[0xe0];
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#if defined(CONFIG_MX51)
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} bank[4];
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#elif defined(CONFIG_MX53)
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} bank[5];
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#endif
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};
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struct fuse_bank0_regs {
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u32 fuse0_7[8];
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u32 uid[8];
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u32 fuse16_23[8];
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#if defined(CONFIG_MX51)
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u32 imei[8];
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#elif defined(CONFIG_MX53)
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u32 gp[8];
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#endif
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};
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struct fuse_bank1_regs {
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u32 fuse0_8[9];
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u32 mac_addr[6];
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u32 fuse15_31[0x11];
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};
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#if defined(CONFIG_MX53)
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struct fuse_bank4_regs {
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u32 fuse0_4[5];
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u32 gp[3];
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u32 fuse8_31[0x18];
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};
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#endif
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#endif /* __ASSEMBLER__*/
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#endif /* __ASM_ARCH_MX5_IMX_REGS_H__ */
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