/*
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* Copyright (c) 2015 MediaTek Inc.
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* Author: Bayi Cheng <bayi.cheng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <linux/math64.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/mtd/mtd.h>
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#include <linux/mtd/partitions.h>
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#include <linux/mtd/spi-nor.h>
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#define MTK_NOR_CMD_REG 0x00
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#define MTK_NOR_CNT_REG 0x04
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#define MTK_NOR_RDSR_REG 0x08
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#define MTK_NOR_RDATA_REG 0x0c
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#define MTK_NOR_RADR0_REG 0x10
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#define MTK_NOR_RADR1_REG 0x14
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#define MTK_NOR_RADR2_REG 0x18
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#define MTK_NOR_WDATA_REG 0x1c
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#define MTK_NOR_PRGDATA0_REG 0x20
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#define MTK_NOR_PRGDATA1_REG 0x24
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#define MTK_NOR_PRGDATA2_REG 0x28
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#define MTK_NOR_PRGDATA3_REG 0x2c
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#define MTK_NOR_PRGDATA4_REG 0x30
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#define MTK_NOR_PRGDATA5_REG 0x34
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#define MTK_NOR_SHREG0_REG 0x38
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#define MTK_NOR_SHREG1_REG 0x3c
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#define MTK_NOR_SHREG2_REG 0x40
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#define MTK_NOR_SHREG3_REG 0x44
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#define MTK_NOR_SHREG4_REG 0x48
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#define MTK_NOR_SHREG5_REG 0x4c
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#define MTK_NOR_SHREG6_REG 0x50
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#define MTK_NOR_SHREG7_REG 0x54
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#define MTK_NOR_SHREG8_REG 0x58
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#define MTK_NOR_SHREG9_REG 0x5c
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#define MTK_NOR_CFG1_REG 0x60
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#define MTK_NOR_CFG2_REG 0x64
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#define MTK_NOR_CFG3_REG 0x68
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#define MTK_NOR_STATUS0_REG 0x70
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#define MTK_NOR_STATUS1_REG 0x74
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#define MTK_NOR_STATUS2_REG 0x78
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#define MTK_NOR_STATUS3_REG 0x7c
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#define MTK_NOR_FLHCFG_REG 0x84
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#define MTK_NOR_TIME_REG 0x94
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#define MTK_NOR_PP_DATA_REG 0x98
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#define MTK_NOR_PREBUF_STUS_REG 0x9c
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#define MTK_NOR_DELSEL0_REG 0xa0
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#define MTK_NOR_DELSEL1_REG 0xa4
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#define MTK_NOR_INTRSTUS_REG 0xa8
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#define MTK_NOR_INTREN_REG 0xac
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#define MTK_NOR_CHKSUM_CTL_REG 0xb8
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#define MTK_NOR_CHKSUM_REG 0xbc
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#define MTK_NOR_CMD2_REG 0xc0
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#define MTK_NOR_WRPROT_REG 0xc4
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#define MTK_NOR_RADR3_REG 0xc8
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#define MTK_NOR_DUAL_REG 0xcc
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#define MTK_NOR_DELSEL2_REG 0xd0
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#define MTK_NOR_DELSEL3_REG 0xd4
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#define MTK_NOR_DELSEL4_REG 0xd8
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/* commands for mtk nor controller */
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#define MTK_NOR_READ_CMD 0x0
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#define MTK_NOR_RDSR_CMD 0x2
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#define MTK_NOR_PRG_CMD 0x4
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#define MTK_NOR_WR_CMD 0x10
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#define MTK_NOR_PIO_WR_CMD 0x90
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#define MTK_NOR_WRSR_CMD 0x20
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#define MTK_NOR_PIO_READ_CMD 0x81
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#define MTK_NOR_WR_BUF_ENABLE 0x1
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#define MTK_NOR_WR_BUF_DISABLE 0x0
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#define MTK_NOR_ENABLE_SF_CMD 0x30
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#define MTK_NOR_DUAD_ADDR_EN 0x8
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#define MTK_NOR_QUAD_READ_EN 0x4
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#define MTK_NOR_DUAL_ADDR_EN 0x2
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#define MTK_NOR_DUAL_READ_EN 0x1
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#define MTK_NOR_DUAL_DISABLE 0x0
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#define MTK_NOR_FAST_READ 0x1
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#define SFLASH_WRBUF_SIZE 128
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/* Can shift up to 48 bits (6 bytes) of TX/RX */
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#define MTK_NOR_MAX_RX_TX_SHIFT 6
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/* can shift up to 56 bits (7 bytes) transfer by MTK_NOR_PRG_CMD */
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#define MTK_NOR_MAX_SHIFT 7
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/* nor controller 4-byte address mode enable bit */
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#define MTK_NOR_4B_ADDR_EN BIT(4)
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/* Helpers for accessing the program data / shift data registers */
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#define MTK_NOR_PRG_REG(n) (MTK_NOR_PRGDATA0_REG + 4 * (n))
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#define MTK_NOR_SHREG(n) (MTK_NOR_SHREG0_REG + 4 * (n))
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struct mtk_nor {
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struct spi_nor nor;
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struct device *dev;
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void __iomem *base; /* nor flash base address */
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struct clk *spi_clk;
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struct clk *nor_clk;
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};
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static void mtk_nor_set_read_mode(struct mtk_nor *mtk_nor)
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{
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struct spi_nor *nor = &mtk_nor->nor;
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switch (nor->read_proto) {
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case SNOR_PROTO_1_1_1:
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_FAST_READ, mtk_nor->base +
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MTK_NOR_CFG1_REG);
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break;
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case SNOR_PROTO_1_1_2:
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA3_REG);
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writeb(MTK_NOR_DUAL_READ_EN, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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case SNOR_PROTO_1_1_4:
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writeb(nor->read_opcode, mtk_nor->base +
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MTK_NOR_PRGDATA4_REG);
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writeb(MTK_NOR_QUAD_READ_EN, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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default:
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writeb(MTK_NOR_DUAL_DISABLE, mtk_nor->base +
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MTK_NOR_DUAL_REG);
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break;
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}
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}
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static int mtk_nor_execute_cmd(struct mtk_nor *mtk_nor, u8 cmdval)
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{
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int reg;
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u8 val = cmdval & 0x1f;
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writeb(cmdval, mtk_nor->base + MTK_NOR_CMD_REG);
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return readl_poll_timeout(mtk_nor->base + MTK_NOR_CMD_REG, reg,
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!(reg & val), 100, 10000);
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}
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static int mtk_nor_do_tx_rx(struct mtk_nor *mtk_nor, u8 op,
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u8 *tx, int txlen, u8 *rx, int rxlen)
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{
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int len = 1 + txlen + rxlen;
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int i, ret, idx;
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if (len > MTK_NOR_MAX_SHIFT)
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return -EINVAL;
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writeb(len * 8, mtk_nor->base + MTK_NOR_CNT_REG);
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/* start at PRGDATA5, go down to PRGDATA0 */
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idx = MTK_NOR_MAX_RX_TX_SHIFT - 1;
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/* opcode */
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writeb(op, mtk_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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/* program TX data */
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for (i = 0; i < txlen; i++, idx--)
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writeb(tx[i], mtk_nor->base + MTK_NOR_PRG_REG(idx));
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/* clear out rest of TX registers */
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while (idx >= 0) {
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writeb(0, mtk_nor->base + MTK_NOR_PRG_REG(idx));
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idx--;
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}
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PRG_CMD);
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if (ret)
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return ret;
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/* restart at first RX byte */
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idx = rxlen - 1;
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/* read out RX data */
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for (i = 0; i < rxlen; i++, idx--)
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rx[i] = readb(mtk_nor->base + MTK_NOR_SHREG(idx));
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return 0;
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}
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/* Do a WRSR (Write Status Register) command */
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static int mtk_nor_wr_sr(struct mtk_nor *mtk_nor, u8 sr)
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{
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writeb(sr, mtk_nor->base + MTK_NOR_PRGDATA5_REG);
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writeb(8, mtk_nor->base + MTK_NOR_CNT_REG);
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return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WRSR_CMD);
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}
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static int mtk_nor_write_buffer_enable(struct mtk_nor *mtk_nor)
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{
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u8 reg;
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/* the bit0 of MTK_NOR_CFG2_REG is pre-fetch buffer
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* 0: pre-fetch buffer use for read
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* 1: pre-fetch buffer use for page program
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*/
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writel(MTK_NOR_WR_BUF_ENABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
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0x01 == (reg & 0x01), 100, 10000);
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}
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static int mtk_nor_write_buffer_disable(struct mtk_nor *mtk_nor)
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{
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u8 reg;
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writel(MTK_NOR_WR_BUF_DISABLE, mtk_nor->base + MTK_NOR_CFG2_REG);
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return readb_poll_timeout(mtk_nor->base + MTK_NOR_CFG2_REG, reg,
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MTK_NOR_WR_BUF_DISABLE == (reg & 0x1), 100,
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10000);
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}
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static void mtk_nor_set_addr_width(struct mtk_nor *mtk_nor)
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{
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u8 val;
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struct spi_nor *nor = &mtk_nor->nor;
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val = readb(mtk_nor->base + MTK_NOR_DUAL_REG);
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switch (nor->addr_width) {
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case 3:
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val &= ~MTK_NOR_4B_ADDR_EN;
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break;
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case 4:
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val |= MTK_NOR_4B_ADDR_EN;
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break;
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default:
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dev_warn(mtk_nor->dev, "Unexpected address width %u.\n",
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nor->addr_width);
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break;
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}
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writeb(val, mtk_nor->base + MTK_NOR_DUAL_REG);
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}
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static void mtk_nor_set_addr(struct mtk_nor *mtk_nor, u32 addr)
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{
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int i;
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mtk_nor_set_addr_width(mtk_nor);
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for (i = 0; i < 3; i++) {
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writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR0_REG + i * 4);
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addr >>= 8;
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}
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/* Last register is non-contiguous */
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writeb(addr & 0xff, mtk_nor->base + MTK_NOR_RADR3_REG);
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}
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static ssize_t mtk_nor_read(struct spi_nor *nor, loff_t from, size_t length,
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u_char *buffer)
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{
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int i, ret;
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int addr = (int)from;
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u8 *buf = (u8 *)buffer;
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struct mtk_nor *mtk_nor = nor->priv;
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/* set mode for fast read mode ,dual mode or quad mode */
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mtk_nor_set_read_mode(mtk_nor);
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mtk_nor_set_addr(mtk_nor, addr);
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for (i = 0; i < length; i++) {
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_READ_CMD);
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if (ret < 0)
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return ret;
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buf[i] = readb(mtk_nor->base + MTK_NOR_RDATA_REG);
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}
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return length;
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}
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static int mtk_nor_write_single_byte(struct mtk_nor *mtk_nor,
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int addr, int length, u8 *data)
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{
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int i, ret;
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mtk_nor_set_addr(mtk_nor, addr);
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for (i = 0; i < length; i++) {
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writeb(*data++, mtk_nor->base + MTK_NOR_WDATA_REG);
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_PIO_WR_CMD);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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static int mtk_nor_write_buffer(struct mtk_nor *mtk_nor, int addr,
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const u8 *buf)
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{
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int i, bufidx, data;
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mtk_nor_set_addr(mtk_nor, addr);
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bufidx = 0;
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for (i = 0; i < SFLASH_WRBUF_SIZE; i += 4) {
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data = buf[bufidx + 3]<<24 | buf[bufidx + 2]<<16 |
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buf[bufidx + 1]<<8 | buf[bufidx];
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bufidx += 4;
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writel(data, mtk_nor->base + MTK_NOR_PP_DATA_REG);
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}
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return mtk_nor_execute_cmd(mtk_nor, MTK_NOR_WR_CMD);
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}
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static ssize_t mtk_nor_write(struct spi_nor *nor, loff_t to, size_t len,
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const u_char *buf)
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{
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int ret;
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struct mtk_nor *mtk_nor = nor->priv;
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size_t i;
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ret = mtk_nor_write_buffer_enable(mtk_nor);
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if (ret < 0) {
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dev_warn(mtk_nor->dev, "write buffer enable failed!\n");
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return ret;
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}
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for (i = 0; i + SFLASH_WRBUF_SIZE <= len; i += SFLASH_WRBUF_SIZE) {
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ret = mtk_nor_write_buffer(mtk_nor, to, buf);
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if (ret < 0) {
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dev_err(mtk_nor->dev, "write buffer failed!\n");
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return ret;
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}
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to += SFLASH_WRBUF_SIZE;
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buf += SFLASH_WRBUF_SIZE;
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}
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ret = mtk_nor_write_buffer_disable(mtk_nor);
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if (ret < 0) {
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dev_warn(mtk_nor->dev, "write buffer disable failed!\n");
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return ret;
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}
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if (i < len) {
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ret = mtk_nor_write_single_byte(mtk_nor, to,
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(int)(len - i), (u8 *)buf);
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if (ret < 0) {
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dev_err(mtk_nor->dev, "write single byte failed!\n");
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return ret;
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}
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}
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return len;
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}
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static int mtk_nor_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
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{
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int ret;
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struct mtk_nor *mtk_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_RDSR:
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ret = mtk_nor_execute_cmd(mtk_nor, MTK_NOR_RDSR_CMD);
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if (ret < 0)
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return ret;
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if (len == 1)
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*buf = readb(mtk_nor->base + MTK_NOR_RDSR_REG);
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else
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dev_err(mtk_nor->dev, "len should be 1 for read status!\n");
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break;
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default:
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ret = mtk_nor_do_tx_rx(mtk_nor, opcode, NULL, 0, buf, len);
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break;
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}
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return ret;
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}
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static int mtk_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
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int len)
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{
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int ret;
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struct mtk_nor *mtk_nor = nor->priv;
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switch (opcode) {
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case SPINOR_OP_WRSR:
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/* We only handle 1 byte */
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ret = mtk_nor_wr_sr(mtk_nor, *buf);
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break;
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default:
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ret = mtk_nor_do_tx_rx(mtk_nor, opcode, buf, len, NULL, 0);
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if (ret)
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dev_warn(mtk_nor->dev, "write reg failure!\n");
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break;
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}
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return ret;
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}
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static void mtk_nor_disable_clk(struct mtk_nor *mtk_nor)
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{
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clk_disable_unprepare(mtk_nor->spi_clk);
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clk_disable_unprepare(mtk_nor->nor_clk);
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}
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static int mtk_nor_enable_clk(struct mtk_nor *mtk_nor)
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{
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int ret;
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ret = clk_prepare_enable(mtk_nor->spi_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(mtk_nor->nor_clk);
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if (ret) {
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clk_disable_unprepare(mtk_nor->spi_clk);
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return ret;
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}
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return 0;
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}
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static int mtk_nor_init(struct mtk_nor *mtk_nor,
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struct device_node *flash_node)
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{
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const struct spi_nor_hwcaps hwcaps = {
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.mask = SNOR_HWCAPS_READ_FAST |
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SNOR_HWCAPS_READ_1_1_2 |
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SNOR_HWCAPS_PP,
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};
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int ret;
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struct spi_nor *nor;
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/* initialize controller to accept commands */
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writel(MTK_NOR_ENABLE_SF_CMD, mtk_nor->base + MTK_NOR_WRPROT_REG);
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nor = &mtk_nor->nor;
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nor->dev = mtk_nor->dev;
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nor->priv = mtk_nor;
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spi_nor_set_flash_node(nor, flash_node);
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/* fill the hooks to spi nor */
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nor->read = mtk_nor_read;
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nor->read_reg = mtk_nor_read_reg;
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nor->write = mtk_nor_write;
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nor->write_reg = mtk_nor_write_reg;
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nor->mtd.name = "mtk_nor";
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/* initialized with NULL */
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ret = spi_nor_scan(nor, NULL, &hwcaps);
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if (ret)
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return ret;
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return mtd_device_register(&nor->mtd, NULL, 0);
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}
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static int mtk_nor_drv_probe(struct platform_device *pdev)
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{
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struct device_node *flash_np;
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struct resource *res;
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int ret;
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struct mtk_nor *mtk_nor;
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if (!pdev->dev.of_node) {
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dev_err(&pdev->dev, "No DT found\n");
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return -EINVAL;
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}
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mtk_nor = devm_kzalloc(&pdev->dev, sizeof(*mtk_nor), GFP_KERNEL);
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if (!mtk_nor)
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return -ENOMEM;
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platform_set_drvdata(pdev, mtk_nor);
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mtk_nor->base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mtk_nor->base))
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return PTR_ERR(mtk_nor->base);
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mtk_nor->spi_clk = devm_clk_get(&pdev->dev, "spi");
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if (IS_ERR(mtk_nor->spi_clk))
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return PTR_ERR(mtk_nor->spi_clk);
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mtk_nor->nor_clk = devm_clk_get(&pdev->dev, "sf");
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if (IS_ERR(mtk_nor->nor_clk))
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return PTR_ERR(mtk_nor->nor_clk);
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mtk_nor->dev = &pdev->dev;
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ret = mtk_nor_enable_clk(mtk_nor);
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if (ret)
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return ret;
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/* only support one attached flash */
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flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
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if (!flash_np) {
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dev_err(&pdev->dev, "no SPI flash device to configure\n");
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ret = -ENODEV;
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goto nor_free;
|
}
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ret = mtk_nor_init(mtk_nor, flash_np);
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|
nor_free:
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if (ret)
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mtk_nor_disable_clk(mtk_nor);
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return ret;
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}
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static int mtk_nor_drv_remove(struct platform_device *pdev)
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{
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struct mtk_nor *mtk_nor = platform_get_drvdata(pdev);
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mtk_nor_disable_clk(mtk_nor);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int mtk_nor_suspend(struct device *dev)
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{
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struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
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mtk_nor_disable_clk(mtk_nor);
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return 0;
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}
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static int mtk_nor_resume(struct device *dev)
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{
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struct mtk_nor *mtk_nor = dev_get_drvdata(dev);
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return mtk_nor_enable_clk(mtk_nor);
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}
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static const struct dev_pm_ops mtk_nor_dev_pm_ops = {
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.suspend = mtk_nor_suspend,
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.resume = mtk_nor_resume,
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};
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#define MTK_NOR_DEV_PM_OPS (&mtk_nor_dev_pm_ops)
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#else
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#define MTK_NOR_DEV_PM_OPS NULL
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#endif
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static const struct of_device_id mtk_nor_of_ids[] = {
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{ .compatible = "mediatek,mt8173-nor"},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, mtk_nor_of_ids);
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static struct platform_driver mtk_nor_driver = {
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.probe = mtk_nor_drv_probe,
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.remove = mtk_nor_drv_remove,
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.driver = {
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.name = "mtk-nor",
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.pm = MTK_NOR_DEV_PM_OPS,
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.of_match_table = mtk_nor_of_ids,
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},
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};
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module_platform_driver(mtk_nor_driver);
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MODULE_LICENSE("GPL v2");
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MODULE_DESCRIPTION("MediaTek SPI NOR Flash Driver");
|
