// SPDX-License-Identifier: GPL-2.0
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/regmap.h>
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#include <linux/sched_clock.h>
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#include <soc/at91/atmel_tcb.h>
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struct atmel_tcb_clksrc {
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struct clocksource clksrc;
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struct clock_event_device clkevt;
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struct regmap *regmap;
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void __iomem *base;
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struct clk *clk[2];
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char name[20];
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int channels[2];
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int bits;
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int irq;
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struct {
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u32 cmr;
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u32 imr;
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u32 rc;
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bool clken;
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} cache[2];
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u32 bmr_cache;
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bool registered;
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bool clk_enabled;
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};
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static struct atmel_tcb_clksrc tc, tce;
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static struct clk *tcb_clk_get(struct device_node *node, int channel)
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{
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struct clk *clk;
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char clk_name[] = "t0_clk";
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clk_name[1] += channel;
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clk = of_clk_get_by_name(node->parent, clk_name);
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if (!IS_ERR(clk))
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return clk;
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return of_clk_get_by_name(node->parent, "t0_clk");
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}
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/*
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* Clockevent device using its own channel
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*/
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static void tc_clkevt2_clk_disable(struct clock_event_device *d)
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{
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clk_disable(tce.clk[0]);
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tce.clk_enabled = false;
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}
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static void tc_clkevt2_clk_enable(struct clock_event_device *d)
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{
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if (tce.clk_enabled)
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return;
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clk_enable(tce.clk[0]);
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tce.clk_enabled = true;
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}
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static int tc_clkevt2_stop(struct clock_event_device *d)
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{
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writel(0xff, tce.base + ATMEL_TC_IDR(tce.channels[0]));
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writel(ATMEL_TC_CCR_CLKDIS, tce.base + ATMEL_TC_CCR(tce.channels[0]));
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return 0;
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}
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static int tc_clkevt2_shutdown(struct clock_event_device *d)
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{
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tc_clkevt2_stop(d);
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if (!clockevent_state_detached(d))
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tc_clkevt2_clk_disable(d);
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return 0;
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}
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/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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* because using one of the divided clocks would usually mean the
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* tick rate can never be less than several dozen Hz (vs 0.5 Hz).
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*
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* A divided clock could be good for high resolution timers, since
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* 30.5 usec resolution can seem "low".
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*/
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static int tc_clkevt2_set_oneshot(struct clock_event_device *d)
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{
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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tc_clkevt2_stop(d);
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tc_clkevt2_clk_enable(d);
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/* slow clock, count up to RC, then irq and stop */
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writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_CPCSTOP |
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ATMEL_TC_CMR_WAVE | ATMEL_TC_CMR_WAVESEL_UPRC,
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tce.base + ATMEL_TC_CMR(tce.channels[0]));
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writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channels[0]));
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return 0;
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}
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static int tc_clkevt2_set_periodic(struct clock_event_device *d)
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{
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if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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tc_clkevt2_stop(d);
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/* By not making the gentime core emulate periodic mode on top
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* of oneshot, we get lower overhead and improved accuracy.
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*/
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tc_clkevt2_clk_enable(d);
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/* slow clock, count up to RC, then irq and restart */
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writel(ATMEL_TC_CMR_TCLK(4) | ATMEL_TC_CMR_WAVE |
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ATMEL_TC_CMR_WAVESEL_UPRC,
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tce.base + ATMEL_TC_CMR(tce.channels[0]));
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writel((32768 + HZ / 2) / HZ, tce.base + ATMEL_TC_RC(tce.channels[0]));
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/* Enable clock and interrupts on RC compare */
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writel(ATMEL_TC_CPCS, tce.base + ATMEL_TC_IER(tce.channels[0]));
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writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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tce.base + ATMEL_TC_CCR(tce.channels[0]));
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return 0;
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}
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static int tc_clkevt2_next_event(unsigned long delta,
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struct clock_event_device *d)
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{
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writel(delta, tce.base + ATMEL_TC_RC(tce.channels[0]));
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writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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tce.base + ATMEL_TC_CCR(tce.channels[0]));
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return 0;
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}
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static irqreturn_t tc_clkevt2_irq(int irq, void *handle)
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{
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unsigned int sr;
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sr = readl(tce.base + ATMEL_TC_SR(tce.channels[0]));
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if (sr & ATMEL_TC_CPCS) {
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tce.clkevt.event_handler(&tce.clkevt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static void tc_clkevt2_suspend(struct clock_event_device *d)
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{
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tce.cache[0].cmr = readl(tce.base + ATMEL_TC_CMR(tce.channels[0]));
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tce.cache[0].imr = readl(tce.base + ATMEL_TC_IMR(tce.channels[0]));
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tce.cache[0].rc = readl(tce.base + ATMEL_TC_RC(tce.channels[0]));
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tce.cache[0].clken = !!(readl(tce.base + ATMEL_TC_SR(tce.channels[0])) &
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ATMEL_TC_CLKSTA);
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}
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static void tc_clkevt2_resume(struct clock_event_device *d)
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{
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/* Restore registers for the channel, RA and RB are not used */
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writel(tce.cache[0].cmr, tc.base + ATMEL_TC_CMR(tce.channels[0]));
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writel(tce.cache[0].rc, tc.base + ATMEL_TC_RC(tce.channels[0]));
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writel(0, tc.base + ATMEL_TC_RA(tce.channels[0]));
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writel(0, tc.base + ATMEL_TC_RB(tce.channels[0]));
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/* Disable all the interrupts */
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writel(0xff, tc.base + ATMEL_TC_IDR(tce.channels[0]));
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/* Reenable interrupts that were enabled before suspending */
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writel(tce.cache[0].imr, tc.base + ATMEL_TC_IER(tce.channels[0]));
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/* Start the clock if it was used */
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if (tce.cache[0].clken)
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writel(ATMEL_TC_CCR_CLKEN | ATMEL_TC_CCR_SWTRG,
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tc.base + ATMEL_TC_CCR(tce.channels[0]));
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}
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static int __init tc_clkevt_register(struct device_node *node,
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struct regmap *regmap, void __iomem *base,
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int channel, int irq, int bits)
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{
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int ret;
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struct clk *slow_clk;
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tce.regmap = regmap;
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tce.base = base;
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tce.channels[0] = channel;
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tce.irq = irq;
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slow_clk = of_clk_get_by_name(node->parent, "slow_clk");
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if (IS_ERR(slow_clk))
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return PTR_ERR(slow_clk);
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ret = clk_prepare_enable(slow_clk);
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if (ret)
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return ret;
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tce.clk[0] = tcb_clk_get(node, tce.channels[0]);
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if (IS_ERR(tce.clk[0])) {
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ret = PTR_ERR(tce.clk[0]);
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goto err_slow;
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}
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snprintf(tce.name, sizeof(tce.name), "%s:%d",
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kbasename(node->parent->full_name), channel);
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tce.clkevt.cpumask = cpumask_of(0);
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tce.clkevt.name = tce.name;
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tce.clkevt.set_next_event = tc_clkevt2_next_event,
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tce.clkevt.set_state_shutdown = tc_clkevt2_shutdown,
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tce.clkevt.set_state_periodic = tc_clkevt2_set_periodic,
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tce.clkevt.set_state_oneshot = tc_clkevt2_set_oneshot,
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tce.clkevt.suspend = tc_clkevt2_suspend,
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tce.clkevt.resume = tc_clkevt2_resume,
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tce.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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tce.clkevt.rating = 140;
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/* try to enable clk to avoid future errors in mode change */
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ret = clk_prepare_enable(tce.clk[0]);
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if (ret)
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goto err_slow;
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clk_disable(tce.clk[0]);
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clockevents_config_and_register(&tce.clkevt, 32768, 1,
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CLOCKSOURCE_MASK(bits));
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ret = request_irq(tce.irq, tc_clkevt2_irq, IRQF_TIMER | IRQF_SHARED,
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tce.clkevt.name, &tce);
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if (ret)
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goto err_clk;
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tce.registered = true;
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return 0;
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err_clk:
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clk_unprepare(tce.clk[0]);
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err_slow:
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clk_disable_unprepare(slow_clk);
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return ret;
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}
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/*
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* Clocksource and clockevent using the same channel(s)
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*/
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static u64 tc_get_cycles(struct clocksource *cs)
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{
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u32 lower, upper;
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do {
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upper = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1]));
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lower = readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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} while (upper != readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[1])));
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return (upper << 16) | lower;
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}
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static u64 tc_get_cycles32(struct clocksource *cs)
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{
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return readl_relaxed(tc.base + ATMEL_TC_CV(tc.channels[0]));
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}
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static u64 notrace tc_sched_clock_read(void)
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{
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return tc_get_cycles(&tc.clksrc);
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}
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static u64 notrace tc_sched_clock_read32(void)
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{
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return tc_get_cycles32(&tc.clksrc);
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}
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static int tcb_clkevt_next_event(unsigned long delta,
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struct clock_event_device *d)
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{
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u32 old, next, cur;
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old = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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next = old + delta;
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writel(next, tc.base + ATMEL_TC_RC(tc.channels[0]));
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cur = readl(tc.base + ATMEL_TC_CV(tc.channels[0]));
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/* check whether the delta elapsed while setting the register */
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if ((next < old && cur < old && cur > next) ||
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(next > old && (cur < old || cur > next))) {
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/*
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* Clear the CPCS bit in the status register to avoid
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* generating a spurious interrupt next time a valid
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* timer event is configured.
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*/
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old = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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return -ETIME;
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}
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writel(ATMEL_TC_CPCS, tc.base + ATMEL_TC_IER(tc.channels[0]));
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return 0;
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}
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static irqreturn_t tc_clkevt_irq(int irq, void *handle)
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{
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unsigned int sr;
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sr = readl(tc.base + ATMEL_TC_SR(tc.channels[0]));
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if (sr & ATMEL_TC_CPCS) {
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tc.clkevt.event_handler(&tc.clkevt);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int tcb_clkevt_oneshot(struct clock_event_device *dev)
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{
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if (clockevent_state_oneshot(dev))
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return 0;
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/*
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* Because both clockevent devices may share the same IRQ, we don't want
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* the less likely one to stay requested
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*/
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return request_irq(tc.irq, tc_clkevt_irq, IRQF_TIMER | IRQF_SHARED,
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tc.name, &tc);
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}
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static int tcb_clkevt_shutdown(struct clock_event_device *dev)
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{
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writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[0]));
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if (tc.bits == 16)
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writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[1]));
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if (!clockevent_state_detached(dev))
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free_irq(tc.irq, &tc);
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return 0;
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}
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static void __init tcb_setup_dual_chan(struct atmel_tcb_clksrc *tc,
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int mck_divisor_idx)
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{
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/* first channel: waveform mode, input mclk/8, clock TIOA on overflow */
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writel(mck_divisor_idx /* likely divide-by-8 */
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| ATMEL_TC_CMR_WAVE
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| ATMEL_TC_CMR_WAVESEL_UP /* free-run */
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| ATMEL_TC_CMR_ACPA(SET) /* TIOA rises at 0 */
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| ATMEL_TC_CMR_ACPC(CLEAR), /* (duty cycle 50%) */
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tc->base + ATMEL_TC_CMR(tc->channels[0]));
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writel(0x0000, tc->base + ATMEL_TC_RA(tc->channels[0]));
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writel(0x8000, tc->base + ATMEL_TC_RC(tc->channels[0]));
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writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
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writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
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/* second channel: waveform mode, input TIOA */
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writel(ATMEL_TC_CMR_XC(tc->channels[1]) /* input: TIOA */
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| ATMEL_TC_CMR_WAVE
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| ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
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tc->base + ATMEL_TC_CMR(tc->channels[1]));
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writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[1])); /* no irqs */
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writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[1]));
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/* chain both channel, we assume the previous channel */
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regmap_write(tc->regmap, ATMEL_TC_BMR,
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ATMEL_TC_BMR_TCXC(1 + tc->channels[1], tc->channels[1]));
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/* then reset all the timers */
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regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
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}
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static void __init tcb_setup_single_chan(struct atmel_tcb_clksrc *tc,
|
int mck_divisor_idx)
|
{
|
/* channel 0: waveform mode, input mclk/8 */
|
writel(mck_divisor_idx /* likely divide-by-8 */
|
| ATMEL_TC_CMR_WAVE
|
| ATMEL_TC_CMR_WAVESEL_UP, /* free-run */
|
tc->base + ATMEL_TC_CMR(tc->channels[0]));
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writel(0xff, tc->base + ATMEL_TC_IDR(tc->channels[0])); /* no irqs */
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writel(ATMEL_TC_CCR_CLKEN, tc->base + ATMEL_TC_CCR(tc->channels[0]));
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|
/* then reset all the timers */
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regmap_write(tc->regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
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}
|
|
static void tc_clksrc_suspend(struct clocksource *cs)
|
{
|
int i;
|
|
for (i = 0; i < 1 + (tc.bits == 16); i++) {
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tc.cache[i].cmr = readl(tc.base + ATMEL_TC_CMR(tc.channels[i]));
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tc.cache[i].imr = readl(tc.base + ATMEL_TC_IMR(tc.channels[i]));
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tc.cache[i].rc = readl(tc.base + ATMEL_TC_RC(tc.channels[i]));
|
tc.cache[i].clken = !!(readl(tc.base +
|
ATMEL_TC_SR(tc.channels[i])) &
|
ATMEL_TC_CLKSTA);
|
}
|
|
if (tc.bits == 16)
|
regmap_read(tc.regmap, ATMEL_TC_BMR, &tc.bmr_cache);
|
}
|
|
static void tc_clksrc_resume(struct clocksource *cs)
|
{
|
int i;
|
|
for (i = 0; i < 1 + (tc.bits == 16); i++) {
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/* Restore registers for the channel, RA and RB are not used */
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writel(tc.cache[i].cmr, tc.base + ATMEL_TC_CMR(tc.channels[i]));
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writel(tc.cache[i].rc, tc.base + ATMEL_TC_RC(tc.channels[i]));
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writel(0, tc.base + ATMEL_TC_RA(tc.channels[i]));
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writel(0, tc.base + ATMEL_TC_RB(tc.channels[i]));
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/* Disable all the interrupts */
|
writel(0xff, tc.base + ATMEL_TC_IDR(tc.channels[i]));
|
/* Reenable interrupts that were enabled before suspending */
|
writel(tc.cache[i].imr, tc.base + ATMEL_TC_IER(tc.channels[i]));
|
|
/* Start the clock if it was used */
|
if (tc.cache[i].clken)
|
writel(ATMEL_TC_CCR_CLKEN, tc.base +
|
ATMEL_TC_CCR(tc.channels[i]));
|
}
|
|
/* in case of dual channel, chain channels */
|
if (tc.bits == 16)
|
regmap_write(tc.regmap, ATMEL_TC_BMR, tc.bmr_cache);
|
/* Finally, trigger all the channels*/
|
regmap_write(tc.regmap, ATMEL_TC_BCR, ATMEL_TC_BCR_SYNC);
|
}
|
|
static int __init tcb_clksrc_register(struct device_node *node,
|
struct regmap *regmap, void __iomem *base,
|
int channel, int channel1, int irq,
|
int bits)
|
{
|
u32 rate, divided_rate = 0;
|
int best_divisor_idx = -1;
|
int i, err = -1;
|
u64 (*tc_sched_clock)(void);
|
|
tc.regmap = regmap;
|
tc.base = base;
|
tc.channels[0] = channel;
|
tc.channels[1] = channel1;
|
tc.irq = irq;
|
tc.bits = bits;
|
|
tc.clk[0] = tcb_clk_get(node, tc.channels[0]);
|
if (IS_ERR(tc.clk[0]))
|
return PTR_ERR(tc.clk[0]);
|
err = clk_prepare_enable(tc.clk[0]);
|
if (err) {
|
pr_debug("can't enable T0 clk\n");
|
goto err_clk;
|
}
|
|
/* How fast will we be counting? Pick something over 5 MHz. */
|
rate = (u32)clk_get_rate(tc.clk[0]);
|
for (i = 0; i < 5; i++) {
|
unsigned int divisor = atmel_tc_divisors[i];
|
unsigned int tmp;
|
|
if (!divisor)
|
continue;
|
|
tmp = rate / divisor;
|
pr_debug("TC: %u / %-3u [%d] --> %u\n", rate, divisor, i, tmp);
|
if (best_divisor_idx > 0) {
|
if (tmp < 5 * 1000 * 1000)
|
continue;
|
}
|
divided_rate = tmp;
|
best_divisor_idx = i;
|
}
|
|
if (tc.bits == 32) {
|
tc.clksrc.read = tc_get_cycles32;
|
tcb_setup_single_chan(&tc, best_divisor_idx);
|
tc_sched_clock = tc_sched_clock_read32;
|
snprintf(tc.name, sizeof(tc.name), "%s:%d",
|
kbasename(node->parent->full_name), tc.channels[0]);
|
} else {
|
tc.clk[1] = tcb_clk_get(node, tc.channels[1]);
|
if (IS_ERR(tc.clk[1]))
|
goto err_disable_t0;
|
|
err = clk_prepare_enable(tc.clk[1]);
|
if (err) {
|
pr_debug("can't enable T1 clk\n");
|
goto err_clk1;
|
}
|
tc.clksrc.read = tc_get_cycles,
|
tcb_setup_dual_chan(&tc, best_divisor_idx);
|
tc_sched_clock = tc_sched_clock_read;
|
snprintf(tc.name, sizeof(tc.name), "%s:%d,%d",
|
kbasename(node->parent->full_name), tc.channels[0],
|
tc.channels[1]);
|
}
|
|
pr_debug("%s at %d.%03d MHz\n", tc.name,
|
divided_rate / 1000000,
|
((divided_rate + 500000) % 1000000) / 1000);
|
|
tc.clksrc.name = tc.name;
|
tc.clksrc.suspend = tc_clksrc_suspend;
|
tc.clksrc.resume = tc_clksrc_resume;
|
tc.clksrc.rating = 200;
|
tc.clksrc.mask = CLOCKSOURCE_MASK(32);
|
tc.clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
|
|
err = clocksource_register_hz(&tc.clksrc, divided_rate);
|
if (err)
|
goto err_disable_t1;
|
|
sched_clock_register(tc_sched_clock, 32, divided_rate);
|
|
tc.registered = true;
|
|
/* Set up and register clockevents */
|
tc.clkevt.name = tc.name;
|
tc.clkevt.cpumask = cpumask_of(0);
|
tc.clkevt.set_next_event = tcb_clkevt_next_event;
|
tc.clkevt.set_state_oneshot = tcb_clkevt_oneshot;
|
tc.clkevt.set_state_shutdown = tcb_clkevt_shutdown;
|
tc.clkevt.features = CLOCK_EVT_FEAT_ONESHOT;
|
tc.clkevt.rating = 125;
|
|
clockevents_config_and_register(&tc.clkevt, divided_rate, 1,
|
BIT(tc.bits) - 1);
|
|
return 0;
|
|
err_disable_t1:
|
if (tc.bits == 16)
|
clk_disable_unprepare(tc.clk[1]);
|
|
err_clk1:
|
if (tc.bits == 16)
|
clk_put(tc.clk[1]);
|
|
err_disable_t0:
|
clk_disable_unprepare(tc.clk[0]);
|
|
err_clk:
|
clk_put(tc.clk[0]);
|
|
pr_err("%s: unable to register clocksource/clockevent\n",
|
tc.clksrc.name);
|
|
return err;
|
}
|
|
static int __init tcb_clksrc_init(struct device_node *node)
|
{
|
const struct of_device_id *match;
|
struct regmap *regmap;
|
void __iomem *tcb_base;
|
u32 channel;
|
int irq, err, chan1 = -1;
|
unsigned bits;
|
|
if (tc.registered && tce.registered)
|
return -ENODEV;
|
|
/*
|
* The regmap has to be used to access registers that are shared
|
* between channels on the same TCB but we keep direct IO access for
|
* the counters to avoid the impact on performance
|
*/
|
regmap = syscon_node_to_regmap(node->parent);
|
if (IS_ERR(regmap))
|
return PTR_ERR(regmap);
|
|
tcb_base = of_iomap(node->parent, 0);
|
if (!tcb_base) {
|
pr_err("%s +%d %s\n", __FILE__, __LINE__, __func__);
|
return -ENXIO;
|
}
|
|
match = of_match_node(atmel_tcb_dt_ids, node->parent);
|
bits = (uintptr_t)match->data;
|
|
err = of_property_read_u32_index(node, "reg", 0, &channel);
|
if (err)
|
return err;
|
|
irq = of_irq_get(node->parent, channel);
|
if (irq < 0) {
|
irq = of_irq_get(node->parent, 0);
|
if (irq < 0)
|
return irq;
|
}
|
|
if (tc.registered)
|
return tc_clkevt_register(node, regmap, tcb_base, channel, irq,
|
bits);
|
|
if (bits == 16) {
|
of_property_read_u32_index(node, "reg", 1, &chan1);
|
if (chan1 == -1) {
|
if (tce.registered) {
|
pr_err("%s: clocksource needs two channels\n",
|
node->parent->full_name);
|
return -EINVAL;
|
} else {
|
return tc_clkevt_register(node, regmap,
|
tcb_base, channel,
|
irq, bits);
|
}
|
}
|
}
|
|
return tcb_clksrc_register(node, regmap, tcb_base, channel, chan1, irq,
|
bits);
|
}
|
TIMER_OF_DECLARE(atmel_tcb_clksrc, "atmel,tcb-timer", tcb_clksrc_init);
|
