/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PKUnity Serial Peripheral Interface (SPI) Registers
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*/
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/*
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* Control reg. 0 SPI_CR0
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*/
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#define SPI_CR0 (PKUNITY_SPI_BASE + 0x0000)
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/*
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* Control reg. 1 SPI_CR1
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*/
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#define SPI_CR1 (PKUNITY_SPI_BASE + 0x0004)
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/*
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* Enable reg SPI_SSIENR
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*/
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#define SPI_SSIENR (PKUNITY_SPI_BASE + 0x0008)
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/*
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* Status reg SPI_SR
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*/
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#define SPI_SR (PKUNITY_SPI_BASE + 0x0028)
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/*
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* Interrupt Mask reg SPI_IMR
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*/
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#define SPI_IMR (PKUNITY_SPI_BASE + 0x002C)
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/*
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* Interrupt Status reg SPI_ISR
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*/
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#define SPI_ISR (PKUNITY_SPI_BASE + 0x0030)
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/*
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* Enable SPI Controller SPI_SSIENR_EN
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*/
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#define SPI_SSIENR_EN FIELD(1, 1, 0)
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/*
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* SPI Busy SPI_SR_BUSY
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*/
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#define SPI_SR_BUSY FIELD(1, 1, 0)
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/*
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* Transmit FIFO Not Full SPI_SR_TFNF
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*/
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#define SPI_SR_TFNF FIELD(1, 1, 1)
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/*
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* Transmit FIFO Empty SPI_SR_TFE
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*/
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#define SPI_SR_TFE FIELD(1, 1, 2)
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/*
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* Receive FIFO Not Empty SPI_SR_RFNE
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*/
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#define SPI_SR_RFNE FIELD(1, 1, 3)
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/*
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* Receive FIFO Full SPI_SR_RFF
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*/
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#define SPI_SR_RFF FIELD(1, 1, 4)
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/*
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* Trans. FIFO Empty Interrupt Status SPI_ISR_TXEIS
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*/
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#define SPI_ISR_TXEIS FIELD(1, 1, 0)
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/*
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* Trans. FIFO Overflow Interrupt Status SPI_ISR_TXOIS
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*/
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#define SPI_ISR_TXOIS FIELD(1, 1, 1)
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/*
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* Receiv. FIFO Underflow Interrupt Status SPI_ISR_RXUIS
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*/
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#define SPI_ISR_RXUIS FIELD(1, 1, 2)
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/*
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* Receiv. FIFO Overflow Interrupt Status SPI_ISR_RXOIS
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*/
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#define SPI_ISR_RXOIS FIELD(1, 1, 3)
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/*
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* Receiv. FIFO Full Interrupt Status SPI_ISR_RXFIS
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*/
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#define SPI_ISR_RXFIS FIELD(1, 1, 4)
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#define SPI_ISR_MSTIS FIELD(1, 1, 5)
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/*
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* Trans. FIFO Empty Interrupt Mask SPI_IMR_TXEIM
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*/
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#define SPI_IMR_TXEIM FIELD(1, 1, 0)
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/*
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* Trans. FIFO Overflow Interrupt Mask SPI_IMR_TXOIM
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*/
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#define SPI_IMR_TXOIM FIELD(1, 1, 1)
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/*
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* Receiv. FIFO Underflow Interrupt Mask SPI_IMR_RXUIM
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*/
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#define SPI_IMR_RXUIM FIELD(1, 1, 2)
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/*
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* Receiv. FIFO Overflow Interrupt Mask SPI_IMR_RXOIM
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*/
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#define SPI_IMR_RXOIM FIELD(1, 1, 3)
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/*
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* Receiv. FIFO Full Interrupt Mask SPI_IMR_RXFIM
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*/
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#define SPI_IMR_RXFIM FIELD(1, 1, 4)
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#define SPI_IMR_MSTIM FIELD(1, 1, 5)
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