/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PKUnity NAND Controller Registers
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*/
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/*
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* ID Reg. 0 NAND_IDR0
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*/
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#define NAND_IDR0 (PKUNITY_NAND_BASE + 0x0000)
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/*
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* ID Reg. 1 NAND_IDR1
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*/
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#define NAND_IDR1 (PKUNITY_NAND_BASE + 0x0004)
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/*
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* ID Reg. 2 NAND_IDR2
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*/
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#define NAND_IDR2 (PKUNITY_NAND_BASE + 0x0008)
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/*
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* ID Reg. 3 NAND_IDR3
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*/
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#define NAND_IDR3 (PKUNITY_NAND_BASE + 0x000C)
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/*
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* Page Address Reg 0 NAND_PAR0
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*/
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#define NAND_PAR0 (PKUNITY_NAND_BASE + 0x0010)
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/*
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* Page Address Reg 1 NAND_PAR1
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*/
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#define NAND_PAR1 (PKUNITY_NAND_BASE + 0x0014)
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/*
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* Page Address Reg 2 NAND_PAR2
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*/
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#define NAND_PAR2 (PKUNITY_NAND_BASE + 0x0018)
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/*
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* ECC Enable Reg NAND_ECCEN
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*/
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#define NAND_ECCEN (PKUNITY_NAND_BASE + 0x001C)
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/*
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* Buffer Reg NAND_BUF
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*/
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#define NAND_BUF (PKUNITY_NAND_BASE + 0x0020)
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/*
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* ECC Status Reg NAND_ECCSR
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*/
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#define NAND_ECCSR (PKUNITY_NAND_BASE + 0x0024)
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/*
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* Command Reg NAND_CMD
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*/
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#define NAND_CMD (PKUNITY_NAND_BASE + 0x0028)
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/*
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* DMA Configure Reg NAND_DMACR
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*/
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#define NAND_DMACR (PKUNITY_NAND_BASE + 0x002C)
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/*
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* Interrupt Reg NAND_IR
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*/
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#define NAND_IR (PKUNITY_NAND_BASE + 0x0030)
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/*
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* Interrupt Mask Reg NAND_IMR
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*/
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#define NAND_IMR (PKUNITY_NAND_BASE + 0x0034)
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/*
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* Chip Enable Reg NAND_CHIPEN
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*/
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#define NAND_CHIPEN (PKUNITY_NAND_BASE + 0x0038)
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/*
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* Address Reg NAND_ADDR
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*/
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#define NAND_ADDR (PKUNITY_NAND_BASE + 0x003C)
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/*
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* Command bits NAND_CMD_CMD_MASK
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*/
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#define NAND_CMD_CMD_MASK FMASK(4, 4)
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#define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
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#define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
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#define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
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#define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
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#define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
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#define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)
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