d) Xilinx IP cores
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The Xilinx EDK toolchain ships with a set of IP cores (devices) for use
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in Xilinx Spartan and Virtex FPGAs. The devices cover the whole range
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of standard device types (network, serial, etc.) and miscellaneous
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devices (gpio, LCD, spi, etc). Also, since these devices are
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implemented within the fpga fabric every instance of the device can be
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synthesised with different options that change the behaviour.
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Each IP-core has a set of parameters which the FPGA designer can use to
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control how the core is synthesized. Historically, the EDK tool would
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extract the device parameters relevant to device drivers and copy them
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into an 'xparameters.h' in the form of #define symbols. This tells the
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device drivers how the IP cores are configured, but it requires the kernel
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to be recompiled every time the FPGA bitstream is resynthesized.
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The new approach is to export the parameters into the device tree and
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generate a new device tree each time the FPGA bitstream changes. The
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parameters which used to be exported as #defines will now become
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properties of the device node. In general, device nodes for IP-cores
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will take the following form:
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(name): (generic-name)@(base-address) {
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compatible = "xlnx,(ip-core-name)-(HW_VER)"
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[, (list of compatible devices), ...];
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reg = <(baseaddr) (size)>;
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interrupt-parent = <&interrupt-controller-phandle>;
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interrupts = < ... >;
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xlnx,(parameter1) = "(string-value)";
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xlnx,(parameter2) = <(int-value)>;
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};
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(generic-name): an open firmware-style name that describes the
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generic class of device. Preferably, this is one word, such
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as 'serial' or 'ethernet'.
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(ip-core-name): the name of the ip block (given after the BEGIN
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directive in system.mhs). Should be in lowercase
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and all underscores '_' converted to dashes '-'.
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(name): is derived from the "PARAMETER INSTANCE" value.
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(parameter#): C_* parameters from system.mhs. The C_ prefix is
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dropped from the parameter name, the name is converted
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to lowercase and all underscore '_' characters are
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converted to dashes '-'.
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(baseaddr): the baseaddr parameter value (often named C_BASEADDR).
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(HW_VER): from the HW_VER parameter.
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(size): the address range size (often C_HIGHADDR - C_BASEADDR + 1).
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Typically, the compatible list will include the exact IP core version
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followed by an older IP core version which implements the same
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interface or any other device with the same interface.
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'reg' and 'interrupts' are all optional properties.
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For example, the following block from system.mhs:
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BEGIN opb_uartlite
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PARAMETER INSTANCE = opb_uartlite_0
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BAUDRATE = 115200
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_CLK_FREQ = 50000000
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PARAMETER C_BASEADDR = 0xEC100000
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PARAMETER C_HIGHADDR = 0xEC10FFFF
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BUS_INTERFACE SOPB = opb_7
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PORT OPB_Clk = CLK_50MHz
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PORT Interrupt = opb_uartlite_0_Interrupt
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PORT RX = opb_uartlite_0_RX
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PORT TX = opb_uartlite_0_TX
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PORT OPB_Rst = sys_bus_reset_0
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END
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becomes the following device tree node:
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opb_uartlite_0: serial@ec100000 {
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device_type = "serial";
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compatible = "xlnx,opb-uartlite-1.00.b";
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reg = <ec100000 10000>;
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interrupt-parent = <&opb_intc_0>;
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interrupts = <1 0>; // got this from the opb_intc parameters
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current-speed = <d#115200>; // standard serial device prop
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clock-frequency = <d#50000000>; // standard serial device prop
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xlnx,data-bits = <8>;
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xlnx,odd-parity = <0>;
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xlnx,use-parity = <0>;
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};
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Some IP cores actually implement 2 or more logical devices. In
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this case, the device should still describe the whole IP core with
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a single node and add a child node for each logical device. The
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ranges property can be used to translate from parent IP-core to the
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registers of each device. In addition, the parent node should be
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compatible with the bus type 'xlnx,compound', and should contain
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#address-cells and #size-cells, as with any other bus. (Note: this
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makes the assumption that both logical devices have the same bus
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binding. If this is not true, then separate nodes should be used
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for each logical device). The 'cell-index' property can be used to
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enumerate logical devices within an IP core. For example, the
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following is the system.mhs entry for the dual ps2 controller found
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on the ml403 reference design.
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BEGIN opb_ps2_dual_ref
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PARAMETER INSTANCE = opb_ps2_dual_ref_0
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_BASEADDR = 0xA9000000
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PARAMETER C_HIGHADDR = 0xA9001FFF
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BUS_INTERFACE SOPB = opb_v20_0
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PORT Sys_Intr1 = ps2_1_intr
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PORT Sys_Intr2 = ps2_2_intr
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PORT Clkin1 = ps2_clk_rx_1
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PORT Clkin2 = ps2_clk_rx_2
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PORT Clkpd1 = ps2_clk_tx_1
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PORT Clkpd2 = ps2_clk_tx_2
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PORT Rx1 = ps2_d_rx_1
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PORT Rx2 = ps2_d_rx_2
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PORT Txpd1 = ps2_d_tx_1
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PORT Txpd2 = ps2_d_tx_2
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END
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It would result in the following device tree nodes:
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opb_ps2_dual_ref_0: opb-ps2-dual-ref@a9000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,compound";
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ranges = <0 a9000000 2000>;
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// If this device had extra parameters, then they would
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// go here.
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ps2@0 {
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compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
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reg = <0 40>;
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interrupt-parent = <&opb_intc_0>;
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interrupts = <3 0>;
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cell-index = <0>;
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};
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ps2@1000 {
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compatible = "xlnx,opb-ps2-dual-ref-1.00.a";
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reg = <1000 40>;
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interrupt-parent = <&opb_intc_0>;
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interrupts = <3 0>;
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cell-index = <0>;
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};
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};
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Also, the system.mhs file defines bus attachments from the processor
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to the devices. The device tree structure should reflect the bus
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attachments. Again an example; this system.mhs fragment:
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BEGIN ppc405_virtex4
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PARAMETER INSTANCE = ppc405_0
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PARAMETER HW_VER = 1.01.a
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BUS_INTERFACE DPLB = plb_v34_0
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BUS_INTERFACE IPLB = plb_v34_0
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END
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BEGIN opb_intc
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PARAMETER INSTANCE = opb_intc_0
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PARAMETER HW_VER = 1.00.c
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PARAMETER C_BASEADDR = 0xD1000FC0
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PARAMETER C_HIGHADDR = 0xD1000FDF
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BUS_INTERFACE SOPB = opb_v20_0
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END
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BEGIN opb_uart16550
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PARAMETER INSTANCE = opb_uart16550_0
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PARAMETER HW_VER = 1.00.d
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PARAMETER C_BASEADDR = 0xa0000000
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PARAMETER C_HIGHADDR = 0xa0001FFF
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BUS_INTERFACE SOPB = opb_v20_0
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END
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BEGIN plb_v34
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PARAMETER INSTANCE = plb_v34_0
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PARAMETER HW_VER = 1.02.a
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END
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BEGIN plb_bram_if_cntlr
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PARAMETER INSTANCE = plb_bram_if_cntlr_0
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BASEADDR = 0xFFFF0000
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PARAMETER C_HIGHADDR = 0xFFFFFFFF
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BUS_INTERFACE SPLB = plb_v34_0
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END
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BEGIN plb2opb_bridge
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PARAMETER INSTANCE = plb2opb_bridge_0
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_RNG0_BASEADDR = 0x20000000
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PARAMETER C_RNG0_HIGHADDR = 0x3FFFFFFF
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PARAMETER C_RNG1_BASEADDR = 0x60000000
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PARAMETER C_RNG1_HIGHADDR = 0x7FFFFFFF
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PARAMETER C_RNG2_BASEADDR = 0x80000000
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PARAMETER C_RNG2_HIGHADDR = 0xBFFFFFFF
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PARAMETER C_RNG3_BASEADDR = 0xC0000000
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PARAMETER C_RNG3_HIGHADDR = 0xDFFFFFFF
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BUS_INTERFACE SPLB = plb_v34_0
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BUS_INTERFACE MOPB = opb_v20_0
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END
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Gives this device tree (some properties removed for clarity):
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plb@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,plb-v34-1.02.a";
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device_type = "ibm,plb";
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ranges; // 1:1 translation
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plb_bram_if_cntrl_0: bram@ffff0000 {
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reg = <ffff0000 10000>;
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}
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opb@20000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <20000000 20000000 20000000
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60000000 60000000 20000000
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80000000 80000000 40000000
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c0000000 c0000000 20000000>;
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opb_uart16550_0: serial@a0000000 {
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reg = <a00000000 2000>;
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};
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opb_intc_0: interrupt-controller@d1000fc0 {
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reg = <d1000fc0 20>;
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};
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};
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};
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That covers the general approach to binding xilinx IP cores into the
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device tree. The following are bindings for specific devices:
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i) Xilinx ML300 Framebuffer
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Simple framebuffer device from the ML300 reference design (also on the
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ML403 reference design as well as others).
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Optional properties:
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- resolution = <xres yres> : pixel resolution of framebuffer. Some
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implementations use a different resolution.
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Default is <d#640 d#480>
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- virt-resolution = <xvirt yvirt> : Size of framebuffer in memory.
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Default is <d#1024 d#480>.
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- rotate-display (empty) : rotate display 180 degrees.
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ii) Xilinx SystemACE
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The Xilinx SystemACE device is used to program FPGAs from an FPGA
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bitstream stored on a CF card. It can also be used as a generic CF
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interface device.
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Optional properties:
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- 8-bit (empty) : Set this property for SystemACE in 8 bit mode
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iii) Xilinx EMAC and Xilinx TEMAC
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Xilinx Ethernet devices. In addition to general xilinx properties
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listed above, nodes for these devices should include a phy-handle
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property, and may include other common network device properties
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like local-mac-address.
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iv) Xilinx Uartlite
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Xilinx uartlite devices are simple fixed speed serial ports.
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Required properties:
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- current-speed : Baud rate of uartlite
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v) Xilinx hwicap
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Xilinx hwicap devices provide access to the configuration logic
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of the FPGA through the Internal Configuration Access Port
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(ICAP). The ICAP enables partial reconfiguration of the FPGA,
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readback of the configuration information, and some control over
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'warm boots' of the FPGA fabric.
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Required properties:
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- xlnx,family : The family of the FPGA, necessary since the
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capabilities of the underlying ICAP hardware
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differ between different families. May be
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'virtex2p', 'virtex4', or 'virtex5'.
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- compatible : should contain "xlnx,xps-hwicap-1.00.a" or
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"xlnx,opb-hwicap-1.00.b".
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vi) Xilinx Uart 16550
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Xilinx UART 16550 devices are very similar to the NS16550 but with
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different register spacing and an offset from the base address.
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Required properties:
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- clock-frequency : Frequency of the clock input
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- reg-offset : A value of 3 is required
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- reg-shift : A value of 2 is required
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vii) Xilinx USB Host controller
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The Xilinx USB host controller is EHCI compatible but with a different
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base address for the EHCI registers, and it is always a big-endian
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USB Host controller. The hardware can be configured as high speed only,
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or high speed/full speed hybrid.
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Required properties:
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- xlnx,support-usb-fs: A value 0 means the core is built as high speed
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only. A value 1 means the core also supports
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full speed devices.
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