// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Rockchip Electronics Co. Ltd.
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*
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* Author: Wenping Zhang <wenping.zhang@rock-chips.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <syscon.h>
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#include <linux/io.h>
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#include "rk_ebc.h"
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#ifdef CONFIG_IRQ
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#include <irq-generic.h>
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#endif
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struct ebc_tcon_priv {
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struct udevice *dev;
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void __iomem *reg;
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u32 *regcache;
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u32 reg_len;
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void *grf;
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void *pmugrf;
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struct clk dclk;
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};
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#define msleep(a) udelay((a) * 1000)
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#define HIWORD_UPDATE(x, l, h) (((x) << (l)) | (GENMASK(h, l) << 16))
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#define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
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#define REG_LOAD_GLOBAL_EN 0x1
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/* ebc register define */
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#define EBC_DSP_START 0x0000 //Frame statrt register
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#define EBC_EPD_CTRL 0x0004 //EPD control register
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#define EBC_DSP_CTRL 0x0008 //Display control register
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#define EBC_DSP_HTIMING0 0x000c //H-Timing setting register0
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#define EBC_DSP_HTIMING1 0x0010 //H-Timing setting register1
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#define EBC_DSP_VTIMING0 0x0014 //V-Timing setting register0
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#define EBC_DSP_VTIMING1 0x0018 //V-Timing setting register1
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#define EBC_DSP_ACT_INFO 0x001c //ACTIVE width/height
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#define EBC_WIN_CTRL 0x0020 //Window ctrl
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#define EBC_WIN_MST0 0x0024 //Current win memory start
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#define EBC_WIN_MST1 0x0028 //Next win memory start
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#define EBC_WIN_VIR 0x002c //Window vir width/height
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#define EBC_WIN_ACT 0x0030 //Window act width/height
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#define EBC_WIN_DSP 0x0034 //Window dsp width/height
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#define EBC_WIN_DSP_ST 0x0038 //Window display start point
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#define EBC_INT_STATUS 0x003c //Interrupt register
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#define EBC_VCOM0 0x0040 //VCOM setting register0
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#define EBC_VCOM1 0x0044 //VCOM setting register1
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#define EBC_VCOM2 0x0048 //VCOM setting register2
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#define EBC_VCOM3 0x004c //VCOM setting register3
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#define EBC_CONFIG_DONE 0x0050 //Config done register
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#define EBC_VNUM 0x0054 //Line flag num
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#define EBC_WIN_MST2 0x0058 //Framecount memory start
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#define EBC_LUT_DATA_ADDR 0x1000 //lut data address
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#define DSP_HTOTAL(x) UPDATE(x, 27, 16)
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#define DSP_HS_END(x) UPDATE(x, 7, 0)
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#define DSP_HACT_END(x) UPDATE(x, 26, 16)
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#define DSP_HACT_ST(x) UPDATE(x, 7, 0)
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#define DSP_VTOTAL(x) UPDATE(x, 26, 16)
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#define DSP_VS_END(x) UPDATE(x, 7, 0)
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#define DSP_VACT_END(x) UPDATE(x, 26, 16)
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#define DSP_VACT_ST(x) UPDATE(x, 7, 0)
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#define DSP_HEIGHT(x) UPDATE(x, 26, 16)
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#define DSP_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN2_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 27, 19)
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#define WIN_EN(x) UPDATE(x, 18, 18)
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#define BURST_REG(x) UPDATE(x, 12, 10)
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#define WIN_FIFO_ALMOST_FULL_LEVEL(x) UPDATE(x, 9, 2)
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#define WIN_FMT(x) UPDATE(x, 1, 0)
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#define WIN_VIR_HEIGHT(x) UPDATE(x, 31, 16)
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#define WIN_VIR_WIDTH(x) UPDATE(x, 15, 0)
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#define WIN_ACT_HEIGHT(x) UPDATE(x, 26, 16)
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#define WIN_ACT_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN_DSP_HEIGHT(x) UPDATE(x, 26, 16)
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#define WIN_DSP_WIDTH(x) UPDATE(x, 11, 0)
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#define WIN_DSP_YST(x) UPDATE(x, 26, 16)
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#define WIN_DSP_XST(x) UPDATE(x, 11, 0)
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#define DSP_OUT_LOW BIT(31)
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#define DSP_EINK_MODE(x) UPDATE(x, 13, 13)
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#define DSP_EINK_MODE_MASK BIT(13)
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#define DSP_SDCE_WIDTH(x) UPDATE(x, 25, 16)
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#define DSP_FRM_TOTAL(x) UPDATE(x, 9, 2)
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#define DSP_FRM_TOTAL_MASK GENMASK(9, 2)
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#define DSP_FRM_START BIT(0)
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#define DSP_FRM_START_MASK BIT(0)
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#define SW_BURST_CTRL BIT(12)
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#define EINK_MODE_SWAP(x) UPDATE(x, 31, 31)
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#define EINK_MODE_FRM_SEL(x) UPDATE(x, 30, 30)
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#define DSP_GD_END(x) UPDATE(x, 26, 16)
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#define DSP_GD_ST(x) UPDATE(x, 15, 8)
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#define DSP_THREE_WIN_MODE(x) UPDATE(x, 7, 7)
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#define THREE_WIN_MODE_MASK BIT(7)
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#define DSP_SDDW_MODE(x) UPDATE(x, 6, 6)
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#define EPD_AUO(x) UPDATE(x, 5, 5)
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#define EPD_PWR(x) UPDATE(x, 4, 2)
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#define EPD_GDRL(x) UPDATE(x, 1, 1)
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#define EPD_SDSHR(x) UPDATE(x, 0, 0)
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#define DSP_SWAP_MODE(x) UPDATE(x, 31, 30)
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#define DSP_SWAP_MODE_MASK GENMASK(31, 30)
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#define DSP_SDCLK_DIV(x) UPDATE(x, 19, 16)
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#define DSP_SDCLK_DIV_MASK GENMASK(19, 16)
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#define DSP_VCOM_MODE(x) UPDATE(x, 27, 27)
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#define DSP_VCOM_MODE_MASK BIT(27)
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#define DSP_UPDATE_MODE(x) UPDATE(x, 29, 29)
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#define DSP_DISPLAY_MODE(x) UPDATE(x, 28, 28)
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#define UPDATE_MODE_MASK BIT(29)
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#define DISPLAY_MODE_MASK BIT(28)
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#define DSP_FRM_INT_NUM(x) UPDATE(x, 19, 12)
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#define FRM_END_INT BIT(0)
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#define DSP_END_INT BIT(1)
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#define DSP_FRM_INT BIT(2)
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#define LINE_FLAG_INT BIT(3)
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#define FRM_END_INT_MASK BIT(4)
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#define DSP_END_INT_MASK BIT(5)
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#define DSP_FRM_INT_MASK BIT(6)
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#define LINE_FLAG_INT_MASK BIT(7)
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#define FRM_END_INT_CLR BIT(8)
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#define DSP_END_INT_CLR BIT(9)
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#define DSP_FRM_INT_CLR BIT(10)
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#define LINE_FLAG_INT_CLR BIT(11)
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#define PMU_BASE_ADDR 0xfdd90000
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#define PMU_PWR_GATE_SFTCON 0xA0
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#define PMU_PWR_DWN_ST 0x98
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#define RGA_PD_OFF BIT(5)
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#define RGA_PD_STAT BIT(5)
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enum ebc_win_data_fmt {
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Y_DATA_4BPP = 0,
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Y_DATA_8BPP = 1,
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RGB888 = 2,
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RGB565 = 3,
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};
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#ifdef CONFIG_IRQ
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#define IRQ_EBC 49
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#endif
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static volatile int last_frame_done = -1;
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static inline void regs_dump(struct ebc_tcon_priv *tcon)
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{
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int i;
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printf("dump registers:\n");
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for (i = 0; i <= EBC_WIN_MST2; i = i + 4) {
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if (!(i % 16))
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printf("\n 0x%p:\t", tcon->reg + i);
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printf("0x%x\t", readl(tcon->reg + i));
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}
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printf("\nlut data:\n");
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for (i = 0x1000; i <= 0x1100; i = i + 4) {
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if (!(i % 16))
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printf("\n 0x%p:\t", tcon->reg + i);
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printf("0x%x\t", readl(tcon->reg + i));
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}
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printf("\n");
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}
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static int ebc_power_domain(int on)
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{
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u32 pd_reg;
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u32 pd_stat;
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int delay = 0;
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if (on) {
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pd_reg = RGA_PD_OFF << 16;
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pd_stat = RGA_PD_STAT;
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} else {
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pd_reg = RGA_PD_OFF | (RGA_PD_OFF << 16);
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pd_stat = ~((u32)RGA_PD_STAT);
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}
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/* enable rga pd for ebc tcon*/
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writel(pd_reg, PMU_BASE_ADDR + PMU_PWR_GATE_SFTCON);
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delay = 1000;
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do {
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udelay(1);
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delay--;
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if (delay == 0) {
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printf("Enable rga pd for ebc failed !\n");
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return -1;
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}
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} while (readl(PMU_BASE_ADDR + PMU_PWR_DWN_ST) & pd_stat);
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return 0;
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}
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static inline void tcon_write(struct ebc_tcon_priv *tcon, unsigned int reg,
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unsigned int value)
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{
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unsigned int *cache = tcon->regcache + (reg >> 2);
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writel(value, tcon->reg + reg);
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*cache = value;
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}
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static inline unsigned int tcon_read(struct ebc_tcon_priv *tcon,
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unsigned int reg)
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{
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return readl(tcon->reg + reg);
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}
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static inline void tcon_update_bits(struct ebc_tcon_priv *tcon,
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unsigned int reg, unsigned int mask,
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unsigned int val)
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{
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unsigned int tmp;
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unsigned int *cache = tcon->regcache + (reg >> 2);
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tmp = *cache & ~mask;
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tmp |= val & mask;
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writel(tmp, tcon->reg + reg);
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*cache = tmp;
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}
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#ifdef CONFIG_IRQ
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static void ebc_irq_handler(int irq, void *data)
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{
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u32 intr_status;
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struct udevice *dev = data;
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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intr_status = readl(tcon->reg + EBC_INT_STATUS);
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if (intr_status & DSP_END_INT) {
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tcon_update_bits(tcon, EBC_INT_STATUS,
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DSP_END_INT_CLR, DSP_END_INT_CLR);
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last_frame_done = 1;
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}
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}
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#endif
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static inline void tcon_cfg_done(struct ebc_tcon_priv *tcon)
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{
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writel(REG_LOAD_GLOBAL_EN, tcon->reg + EBC_CONFIG_DONE);
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}
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static int ebc_tcon_enable(struct udevice *dev, struct ebc_panel *panel)
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{
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int ret;
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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u32 width, height, vir_width, vir_height;
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if (panel->rearrange) {
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width = panel->width * 2;
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height = panel->height / 2;
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vir_width = panel->vir_width * 2;
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vir_height = panel->vir_height / 2;
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} else {
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width = panel->width;
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height = panel->height;
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vir_width = panel->vir_width;
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vir_height = panel->vir_height;
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}
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/* panel timing and win info config */
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tcon_write(tcon, EBC_DSP_HTIMING0,
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DSP_HTOTAL(panel->lsl + panel->lbl + panel->ldl +
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panel->lel) | DSP_HS_END(panel->lsl));
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tcon_write(tcon, EBC_DSP_HTIMING1,
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DSP_HACT_END(panel->lsl + panel->lbl + panel->ldl) |
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DSP_HACT_ST(panel->lsl + panel->lbl - 1));
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tcon_write(tcon, EBC_DSP_VTIMING0,
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DSP_VTOTAL(panel->fsl + panel->fbl + panel->fdl +
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panel->fel) | DSP_VS_END(panel->fsl));
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tcon_write(tcon, EBC_DSP_VTIMING1,
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DSP_VACT_END(panel->fsl + panel->fbl + panel->fdl) |
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DSP_VACT_ST(panel->fsl + panel->fbl));
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tcon_write(tcon, EBC_DSP_ACT_INFO,
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DSP_HEIGHT(height) |
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DSP_WIDTH(width));
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tcon_write(tcon, EBC_WIN_VIR,
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WIN_VIR_HEIGHT(vir_height) |
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WIN_VIR_WIDTH(vir_width));
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tcon_write(tcon, EBC_WIN_ACT,
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WIN_ACT_HEIGHT(height) |
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WIN_ACT_WIDTH(width));
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tcon_write(tcon, EBC_WIN_DSP,
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WIN_DSP_HEIGHT(height) |
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WIN_DSP_WIDTH(width));
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tcon_write(tcon, EBC_WIN_DSP_ST,
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WIN_DSP_YST(panel->fsl + panel->fbl) |
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WIN_DSP_XST(panel->lsl + panel->lbl));
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/* win2 fifo is 512x128, win fifo is 256x128,
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* we set fifo almost value (fifo_size - 16)
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* burst_reg = 7 mean ahb burst is incr16
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*/
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tcon_write(tcon, EBC_WIN_CTRL,
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WIN2_FIFO_ALMOST_FULL_LEVEL(496) | WIN_EN(1) |
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BURST_REG(7) | WIN_FIFO_ALMOST_FULL_LEVEL(240) |
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WIN_FMT(Y_DATA_4BPP));
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/*
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* EBC_EPD_CTRL info:
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* DSP_GD_ST: GCLK rising edge point(SCLK), which count from
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* the rasing edge of hsync(spec is wrong, count
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* from rasing edge of hsync, not falling edge of hsync)
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* DSP_GD_END : GCLK falling edge point(SCLK), which count from
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* the rasing edge of hsync
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* DSP_THREE_WIN_MODE: 0: lut mode or direct mode; 1: three win mode
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* DSP_SDDW_MODE: 0: 8 bit data output; 1: 16 bit data output
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* EPD_AUO: 0: EINK; 1:AUO
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* EPD_GDRL: gate scanning direction: 1:button to top 0:top to button
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* EPD_SDSHR: source scanning direction 1:right to left 0:left to right
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*/
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tcon_write(tcon, EBC_EPD_CTRL,
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EINK_MODE_SWAP(1) |
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DSP_GD_ST(panel->lsl + panel->gdck_sta) |
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DSP_GD_END(panel->lsl + panel->gdck_sta + panel->lgonl) |
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DSP_THREE_WIN_MODE(0) |
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DSP_SDDW_MODE(!!panel->panel_16bit) |
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EPD_AUO(0) |
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EPD_GDRL(1) |
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EPD_SDSHR(1));
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tcon_write(tcon, EBC_DSP_START,
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DSP_SDCE_WIDTH(panel->ldl) | SW_BURST_CTRL);
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tcon_write(tcon, EBC_DSP_CTRL,
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DSP_SWAP_MODE(panel->panel_16bit ? 2 : 3) |
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DSP_VCOM_MODE(1) |
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DSP_SDCLK_DIV(panel->panel_16bit ? 7 : 3));
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tcon_cfg_done(tcon);
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ret = clk_set_rate(&tcon->dclk, panel->sdck * ((panel->panel_16bit ? 7 : 3) + 1));
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if (ret < 0) {
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printf("%s: set clock rate failed, %d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int ebc_tcon_disable(struct udevice *dev)
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{
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return 0;
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}
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static int ebc_tcon_dsp_mode_set(struct udevice *dev, int update_mode,
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int display_mode, int three_win_mode,
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int eink_mode)
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{
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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tcon_update_bits(tcon, EBC_DSP_CTRL,
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UPDATE_MODE_MASK | DISPLAY_MODE_MASK,
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DSP_UPDATE_MODE(!!update_mode) |
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DSP_DISPLAY_MODE(!!display_mode));
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tcon_update_bits(tcon, EBC_EPD_CTRL, THREE_WIN_MODE_MASK,
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DSP_THREE_WIN_MODE(!!three_win_mode));
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/* always set frm start bit 0 before real frame start */
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tcon_update_bits(tcon, EBC_DSP_START,
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DSP_EINK_MODE_MASK | DSP_FRM_START_MASK,
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DSP_EINK_MODE(!!eink_mode));
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tcon_cfg_done(tcon);
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return 0;
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}
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static int ebc_tcon_image_addr_set(struct udevice *dev, u32 pre_image_addr,
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u32 cur_image_addr)
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{
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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tcon_write(tcon, EBC_WIN_MST0, pre_image_addr);
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tcon_write(tcon, EBC_WIN_MST1, cur_image_addr);
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tcon_cfg_done(tcon);
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return 0;
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}
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static int ebc_tcon_frame_addr_set(struct udevice *dev, u32 frame_addr)
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{
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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tcon_write(tcon, EBC_WIN_MST2, frame_addr);
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tcon_cfg_done(tcon);
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return 0;
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}
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static int ebc_tcon_lut_data_set(struct udevice *dev, unsigned int *lut_data,
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int frame_count, int lut_32)
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{
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int i, lut_size;
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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if ((!lut_32 && frame_count > 256) || (lut_32 && frame_count > 64)) {
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dev_err(tcon->dev, "frame count over flow\n");
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return -1;
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}
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if (lut_32)
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lut_size = frame_count * 64;
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else
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lut_size = frame_count * 16;
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for (i = 0; i < lut_size; i++)
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tcon_write(tcon, EBC_LUT_DATA_ADDR + (i * 4), lut_data[i]);
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tcon_cfg_done(tcon);
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return 0;
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}
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static int wait_for_last_frame_complete(struct udevice *dev)
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{
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#ifndef CONFIG_IRQ
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u32 intr_status;
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#endif
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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#ifdef CONFIG_IRQ
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while (1) {
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if ((last_frame_done == -1) || (last_frame_done == 1))
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break;
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msleep(1);
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}
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#else
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/* wait for frame display end*/
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while (1) {
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/* first frame don't need to wait*/
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if (last_frame_done == -1)
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break;
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intr_status = readl(tcon->reg + EBC_INT_STATUS);
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if (intr_status & DSP_END_INT)
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break;
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msleep(1);
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}
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#endif
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tcon_update_bits(tcon, EBC_INT_STATUS,
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DSP_END_INT_CLR, DSP_END_INT_CLR);
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return 0;
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}
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static int ebc_tcon_frame_start(struct udevice *dev, int frame_total)
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{
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struct ebc_tcon_priv *tcon = dev_get_priv(dev);
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tcon_write(tcon, EBC_INT_STATUS,
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LINE_FLAG_INT_MASK | DSP_FRM_INT_MASK | FRM_END_INT_MASK);
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tcon_update_bits(tcon, EBC_DSP_START,
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DSP_FRM_TOTAL_MASK, DSP_FRM_TOTAL(frame_total - 1));
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tcon_cfg_done(tcon);
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tcon_update_bits(tcon, EBC_DSP_START,
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DSP_FRM_START_MASK, DSP_FRM_START);
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last_frame_done = 0;
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return 0;
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}
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static int rk_ebc_tcon_probe(struct udevice *dev)
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{
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int ret;
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struct ebc_tcon_priv *priv = dev_get_priv(dev);
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/*Enable PD first*/
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ret = ebc_power_domain(1);
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if (ret) {
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printf("%s, enable pd failed\n", __func__);
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return -1;
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}
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priv->dev = dev;
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ret = clk_get_by_index(dev, 1, &priv->dclk);
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if (ret < 0) {
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printf("%s get clock fail! %d\n", __func__, ret);
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return -EINVAL;
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}
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#ifdef CONFIG_IRQ
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irq_install_handler(IRQ_EBC, ebc_irq_handler, dev);
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irq_handler_enable(IRQ_EBC);
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#endif
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return 0;
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}
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const struct rk_ebc_tcon_ops ebc_tcon_funcs = {
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.enable = ebc_tcon_enable,
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.disable = ebc_tcon_disable,
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.dsp_mode_set = ebc_tcon_dsp_mode_set,
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.image_addr_set = ebc_tcon_image_addr_set,
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.frame_addr_set = ebc_tcon_frame_addr_set,
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.lut_data_set = ebc_tcon_lut_data_set,
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.frame_start = ebc_tcon_frame_start,
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.wait_for_last_frame_complete = wait_for_last_frame_complete,
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};
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static int rk_ebc_tcon_ofdata_to_platdata(struct udevice *dev)
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{
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fdt_size_t size;
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fdt_addr_t addr;
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struct ebc_tcon_priv *priv = dev_get_priv(dev);
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priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
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if (priv->grf <= 0) {
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debug("%s: Get syscon grf failed (ret=%p)\n",
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__func__, priv->grf);
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return -ENXIO;
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}
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priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
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if (priv->pmugrf <= 0) {
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debug("%s: Get syscon pmugrf failed (ret=%p)\n",
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__func__, priv->grf);
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return -ENXIO;
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}
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addr = dev_read_addr_size(dev, "reg", &size);
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if (addr == FDT_ADDR_T_NONE) {
|
debug("%s: Get ebc_tcon address failed\n", __func__);
|
return -ENXIO;
|
}
|
|
priv->reg = ioremap(addr, size);
|
priv->reg_len = size;
|
priv->regcache = malloc(size);
|
memset(priv->regcache, 0, size);
|
return 0;
|
}
|
|
static const struct udevice_id ebc_tcon_ids[] = {
|
{ .compatible = "rockchip,rk3568-ebc-tcon" },
|
{ }
|
};
|
|
U_BOOT_DRIVER(rk_ebc_tcon) = {
|
.name = "rk_ebc_tcon",
|
.id = UCLASS_EBC,
|
.of_match = ebc_tcon_ids,
|
.ofdata_to_platdata = rk_ebc_tcon_ofdata_to_platdata,
|
.probe = rk_ebc_tcon_probe,
|
.ops = &ebc_tcon_funcs,
|
.priv_auto_alloc_size = sizeof(struct ebc_tcon_priv),
|
};
|
|
UCLASS_DRIVER(ebc_tcon) = {
|
.id = UCLASS_EBC,
|
.name = "ebc_tcon",
|
};
|
