/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright(c) 2008 - 2010 Realtek Corporation. All rights reserved.
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*
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* Contact Information: wlanfae <wlanfae@realtek.com>
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*/
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#ifndef _R819XU_PHYREG_H
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#define _R819XU_PHYREG_H
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#define RF_DATA 0x1d4
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#define rPMAC_Reset 0x100
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#define rPMAC_TxStart 0x104
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#define rPMAC_TxLegacySIG 0x108
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#define rPMAC_TxHTSIG1 0x10c
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#define rPMAC_TxHTSIG2 0x110
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#define rPMAC_PHYDebug 0x114
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#define rPMAC_TxPacketNum 0x118
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#define rPMAC_TxIdle 0x11c
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#define rPMAC_TxMACHeader0 0x120
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#define rPMAC_TxMACHeader1 0x124
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#define rPMAC_TxMACHeader2 0x128
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#define rPMAC_TxMACHeader3 0x12c
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#define rPMAC_TxMACHeader4 0x130
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#define rPMAC_TxMACHeader5 0x134
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#define rPMAC_TxDataType 0x138
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#define rPMAC_TxRandomSeed 0x13c
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#define rPMAC_CCKPLCPPreamble 0x140
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#define rPMAC_CCKPLCPHeader 0x144
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#define rPMAC_CCKCRC16 0x148
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#define rPMAC_OFDMRxCRC32OK 0x170
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#define rPMAC_OFDMRxCRC32Er 0x174
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#define rPMAC_OFDMRxParityEr 0x178
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#define rPMAC_OFDMRxCRC8Er 0x17c
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#define rPMAC_CCKCRxRC16Er 0x180
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#define rPMAC_CCKCRxRC32Er 0x184
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#define rPMAC_CCKCRxRC32OK 0x188
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#define rPMAC_TxStatus 0x18c
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#define MCS_TXAGC 0x340
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#define CCK_TXAGC 0x348
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/* Mac block on/off control register */
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#define MacBlkCtrl 0x403
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#define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */
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#define rFPGA0_TxInfo 0x804
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#define rFPGA0_PSDFunction 0x808
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#define rFPGA0_TxGainStage 0x80c
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#define rFPGA0_RFTiming1 0x810
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#define rFPGA0_RFTiming2 0x814
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#define rFPGA0_XA_HSSIParameter1 0x820
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#define rFPGA0_XA_HSSIParameter2 0x824
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#define rFPGA0_XB_HSSIParameter1 0x828
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#define rFPGA0_XB_HSSIParameter2 0x82c
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#define rFPGA0_XC_HSSIParameter1 0x830
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#define rFPGA0_XC_HSSIParameter2 0x834
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#define rFPGA0_XD_HSSIParameter1 0x838
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#define rFPGA0_XD_HSSIParameter2 0x83c
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#define rFPGA0_XA_LSSIParameter 0x840
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#define rFPGA0_XB_LSSIParameter 0x844
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#define rFPGA0_XC_LSSIParameter 0x848
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#define rFPGA0_XD_LSSIParameter 0x84c
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#define rFPGA0_RFWakeUpParameter 0x850
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#define rFPGA0_RFSleepUpParameter 0x854
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#define rFPGA0_XAB_SwitchControl 0x858
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#define rFPGA0_XCD_SwitchControl 0x85c
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#define rFPGA0_XA_RFInterfaceOE 0x860
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#define rFPGA0_XB_RFInterfaceOE 0x864
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#define rFPGA0_XC_RFInterfaceOE 0x868
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#define rFPGA0_XD_RFInterfaceOE 0x86c
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#define rFPGA0_XAB_RFInterfaceSW 0x870
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#define rFPGA0_XCD_RFInterfaceSW 0x874
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#define rFPGA0_XAB_RFParameter 0x878
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#define rFPGA0_XCD_RFParameter 0x87c
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#define rFPGA0_AnalogParameter1 0x880
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#define rFPGA0_AnalogParameter2 0x884
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#define rFPGA0_AnalogParameter3 0x888
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#define rFPGA0_AnalogParameter4 0x88c
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#define rFPGA0_XA_LSSIReadBack 0x8a0
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#define rFPGA0_XB_LSSIReadBack 0x8a4
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#define rFPGA0_XC_LSSIReadBack 0x8a8
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#define rFPGA0_XD_LSSIReadBack 0x8ac
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#define rFPGA0_PSDReport 0x8b4
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#define rFPGA0_XAB_RFInterfaceRB 0x8e0
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#define rFPGA0_XCD_RFInterfaceRB 0x8e4
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/* Page 9 - RF mode & OFDM TxSC */
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#define rFPGA1_RFMOD 0x900
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#define rFPGA1_TxBlock 0x904
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#define rFPGA1_DebugSelect 0x908
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#define rFPGA1_TxInfo 0x90c
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#define rCCK0_System 0xa00
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#define rCCK0_AFESetting 0xa04
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#define rCCK0_CCA 0xa08
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/* AGC default value, saturation level */
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#define rCCK0_RxAGC1 0xa0c
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#define rCCK0_RxAGC2 0xa10 /* AGC & DAGC */
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#define rCCK0_RxHP 0xa14
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/* Timing recovery & channel estimation threshold */
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#define rCCK0_DSPParameter1 0xa18
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#define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
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#define rCCK0_TxFilter1 0xa20
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#define rCCK0_TxFilter2 0xa24
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#define rCCK0_DebugPort 0xa28 /* Debug port and TX filter 3 */
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#define rCCK0_FalseAlarmReport 0xa2c
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#define rCCK0_TRSSIReport 0xa50
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#define rCCK0_RxReport 0xa54
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#define rCCK0_FACounterLower 0xa5c
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#define rCCK0_FACounterUpper 0xa58
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#define rOFDM0_LSTF 0xc00
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#define rOFDM0_TRxPathEnable 0xc04
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#define rOFDM0_TRMuxPar 0xc08
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#define rOFDM0_TRSWIsolation 0xc0c
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/* RxIQ DC offset, Rx digital filter, DC notch filter */
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#define rOFDM0_XARxAFE 0xc10
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#define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imbalance matrix */
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#define rOFDM0_XBRxAFE 0xc18
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#define rOFDM0_XBRxIQImbalance 0xc1c
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#define rOFDM0_XCRxAFE 0xc20
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#define rOFDM0_XCRxIQImbalance 0xc24
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#define rOFDM0_XDRxAFE 0xc28
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#define rOFDM0_XDRxIQImbalance 0xc2c
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#define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */
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#define rOFDM0_RxDetector2 0xc34 /* SBD */
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#define rOFDM0_RxDetector3 0xc38 /* Frame Sync */
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/* PD, SBD, Frame Sync & Short-GI */
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#define rOFDM0_RxDetector4 0xc3c
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#define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
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#define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
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#define rOFDM0_CCADropThreshold 0xc48
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#define rOFDM0_ECCAThreshold 0xc4c /* Energy CCA */
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#define rOFDM0_XAAGCCore1 0xc50
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#define rOFDM0_XAAGCCore2 0xc54
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#define rOFDM0_XBAGCCore1 0xc58
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#define rOFDM0_XBAGCCore2 0xc5c
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#define rOFDM0_XCAGCCore1 0xc60
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#define rOFDM0_XCAGCCore2 0xc64
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#define rOFDM0_XDAGCCore1 0xc68
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#define rOFDM0_XDAGCCore2 0xc6c
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#define rOFDM0_AGCParameter1 0xc70
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#define rOFDM0_AGCParameter2 0xc74
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#define rOFDM0_AGCRSSITable 0xc78
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#define rOFDM0_HTSTFAGC 0xc7c
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#define rOFDM0_XATxIQImbalance 0xc80
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#define rOFDM0_XATxAFE 0xc84
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#define rOFDM0_XBTxIQImbalance 0xc88
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#define rOFDM0_XBTxAFE 0xc8c
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#define rOFDM0_XCTxIQImbalance 0xc90
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#define rOFDM0_XCTxAFE 0xc94
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#define rOFDM0_XDTxIQImbalance 0xc98
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#define rOFDM0_XDTxAFE 0xc9c
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#define rOFDM0_RxHPParameter 0xce0
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#define rOFDM0_TxPseudoNoiseWgt 0xce4
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#define rOFDM0_FrameSync 0xcf0
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#define rOFDM0_DFSReport 0xcf4
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#define rOFDM0_TxCoeff1 0xca4
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#define rOFDM0_TxCoeff2 0xca8
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#define rOFDM0_TxCoeff3 0xcac
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#define rOFDM0_TxCoeff4 0xcb0
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#define rOFDM0_TxCoeff5 0xcb4
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#define rOFDM0_TxCoeff6 0xcb8
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#define rOFDM1_LSTF 0xd00
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#define rOFDM1_TRxPathEnable 0xd04
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#define rOFDM1_CFO 0xd08
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#define rOFDM1_CSI1 0xd10
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#define rOFDM1_SBD 0xd14
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#define rOFDM1_CSI2 0xd18
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#define rOFDM1_CFOTracking 0xd2c
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#define rOFDM1_TRxMesaure1 0xd34
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#define rOFDM1_IntfDet 0xd3c
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#define rOFDM1_PseudoNoiseStateAB 0xd50
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#define rOFDM1_PseudoNoiseStateCD 0xd54
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#define rOFDM1_RxPseudoNoiseWgt 0xd58
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#define rOFDM_PHYCounter1 0xda0 /* cca, parity fail */
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#define rOFDM_PHYCounter2 0xda4 /* rate illegal, crc8 fail */
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#define rOFDM_PHYCounter3 0xda8 /* MCS not supported */
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#define rOFDM_ShortCFOAB 0xdac
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#define rOFDM_ShortCFOCD 0xdb0
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#define rOFDM_LongCFOAB 0xdb4
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#define rOFDM_LongCFOCD 0xdb8
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#define rOFDM_TailCFOAB 0xdbc
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#define rOFDM_TailCFOCD 0xdc0
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#define rOFDM_PWMeasure1 0xdc4
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#define rOFDM_PWMeasure2 0xdc8
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#define rOFDM_BWReport 0xdcc
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#define rOFDM_AGCReport 0xdd0
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#define rOFDM_RxSNR 0xdd4
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#define rOFDM_RxEVMCSI 0xdd8
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#define rOFDM_SIGReport 0xddc
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#define rTxAGC_Rate18_06 0xe00
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#define rTxAGC_Rate54_24 0xe04
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#define rTxAGC_CCK_Mcs32 0xe08
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#define rTxAGC_Mcs03_Mcs00 0xe10
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#define rTxAGC_Mcs07_Mcs04 0xe14
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#define rTxAGC_Mcs11_Mcs08 0xe18
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#define rTxAGC_Mcs15_Mcs12 0xe1c
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#define rZebra1_HSSIEnable 0x0
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#define rZebra1_TRxEnable1 0x1
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#define rZebra1_TRxEnable2 0x2
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#define rZebra1_AGC 0x4
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#define rZebra1_ChargePump 0x5
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#define rZebra1_Channel 0x7
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#define rZebra1_TxGain 0x8
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#define rZebra1_TxLPF 0x9
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#define rZebra1_RxLPF 0xb
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#define rZebra1_RxHPFCorner 0xc
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/* Zebra 4 */
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#define rGlobalCtrl 0
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#define rRTL8256_TxLPF 19
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#define rRTL8256_RxLPF 11
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/* RTL8258 */
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#define rRTL8258_TxLPF 0x11
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#define rRTL8258_RxLPF 0x13
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#define rRTL8258_RSSILPF 0xa
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/* Bit Mask - Page 1*/
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#define bBBResetB 0x100
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#define bGlobalResetB 0x200
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#define bOFDMTxStart 0x4
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#define bCCKTxStart 0x8
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#define bCRC32Debug 0x100
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#define bPMACLoopback 0x10
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#define bTxLSIG 0xffffff
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#define bOFDMTxRate 0xf
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#define bOFDMTxReserved 0x10
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#define bOFDMTxLength 0x1ffe0
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#define bOFDMTxParity 0x20000
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#define bTxHTSIG1 0xffffff
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#define bTxHTMCSRate 0x7f
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#define bTxHTBW 0x80
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#define bTxHTLength 0xffff00
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#define bTxHTSIG2 0xffffff
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#define bTxHTSmoothing 0x1
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#define bTxHTSounding 0x2
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#define bTxHTReserved 0x4
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#define bTxHTAggreation 0x8
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#define bTxHTSTBC 0x30
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#define bTxHTAdvanceCoding 0x40
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#define bTxHTShortGI 0x80
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#define bTxHTNumberHT_LTF 0x300
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#define bTxHTCRC8 0x3fc00
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#define bCounterReset 0x10000
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#define bNumOfOFDMTx 0xffff
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#define bNumOfCCKTx 0xffff0000
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#define bTxIdleInterval 0xffff
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#define bOFDMService 0xffff0000
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#define bTxMACHeader 0xffffffff
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#define bTxDataInit 0xff
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#define bTxHTMode 0x100
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#define bTxDataType 0x30000
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#define bTxRandomSeed 0xffffffff
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#define bCCKTxPreamble 0x1
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#define bCCKTxSFD 0xffff0000
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#define bCCKTxSIG 0xff
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#define bCCKTxService 0xff00
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#define bCCKLengthExt 0x8000
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#define bCCKTxLength 0xffff0000
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#define bCCKTxCRC16 0xffff
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#define bCCKTxStatus 0x1
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#define bOFDMTxStatus 0x2
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/* Bit Mask - Page 8 */
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#define bRFMOD 0x1
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#define bJapanMode 0x2
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#define bCCKTxSC 0x30
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#define bCCKEn 0x1000000
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#define bOFDMEn 0x2000000
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#define bOFDMRxADCPhase 0x10000
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#define bOFDMTxDACPhase 0x40000
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#define bXATxAGC 0x3f
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#define bXBTxAGC 0xf00
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#define bXCTxAGC 0xf000
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#define bXDTxAGC 0xf0000
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#define bPAStart 0xf0000000
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#define bTRStart 0x00f00000
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#define bRFStart 0x0000f000
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#define bBBStart 0x000000f0
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#define bBBCCKStart 0x0000000f
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/* Bit Mask - rFPGA0_RFTiming2 */
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#define bPAEnd 0xf
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#define bTREnd 0x0f000000
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#define bRFEnd 0x000f0000
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/* T2R */
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#define bCCAMask 0x000000f0
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#define bR2RCCAMask 0x00000f00
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#define bHSSI_R2TDelay 0xf8000000
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#define bHSSI_T2RDelay 0xf80000
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/* Channel gain at continue TX. */
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#define bContTxHSSI 0x400
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#define bIGFromCCK 0x200
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#define bAGCAddress 0x3f
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#define bRxHPTx 0x7000
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#define bRxHPT2R 0x38000
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#define bRxHPCCKIni 0xc0000
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#define bAGCTxCode 0xc00000
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#define bAGCRxCode 0x300000
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#define b3WireDataLength 0x800
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#define b3WireAddressLength 0x400
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#define b3WireRFPowerDown 0x1
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/*#define bHWSISelect 0x8 */
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#define b5GPAPEPolarity 0x40000000
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#define b2GPAPEPolarity 0x80000000
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#define bRFSW_TxDefaultAnt 0x3
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#define bRFSW_TxOptionAnt 0x30
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#define bRFSW_RxDefaultAnt 0x300
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#define bRFSW_RxOptionAnt 0x3000
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#define bRFSI_3WireData 0x1
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#define bRFSI_3WireClock 0x2
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#define bRFSI_3WireLoad 0x4
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#define bRFSI_3WireRW 0x8
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/* 3-wire total control */
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#define bRFSI_3Wire 0xf
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#define bRFSI_RFENV 0x10
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#define bRFSI_TRSW 0x20
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#define bRFSI_TRSWB 0x40
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#define bRFSI_ANTSW 0x100
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#define bRFSI_ANTSWB 0x200
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#define bRFSI_PAPE 0x400
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#define bRFSI_PAPE5G 0x800
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#define bBandSelect 0x1
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#define bHTSIG2_GI 0x80
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#define bHTSIG2_Smoothing 0x01
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#define bHTSIG2_Sounding 0x02
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#define bHTSIG2_Aggreaton 0x08
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#define bHTSIG2_STBC 0x30
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#define bHTSIG2_AdvCoding 0x40
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#define bHTSIG2_NumOfHTLTF 0x300
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#define bHTSIG2_CRC8 0x3fc
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#define bHTSIG1_MCS 0x7f
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#define bHTSIG1_BandWidth 0x80
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#define bHTSIG1_HTLength 0xffff
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#define bLSIG_Rate 0xf
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#define bLSIG_Reserved 0x10
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#define bLSIG_Length 0x1fffe
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#define bLSIG_Parity 0x20
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#define bCCKRxPhase 0x4
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#define bLSSIReadAddress 0x3f000000 /* LSSI "read" address */
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#define bLSSIReadEdge 0x80000000 /* LSSI "read" edge signal */
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#define bLSSIReadBackData 0xfff
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#define bLSSIReadOKFlag 0x1000
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#define bCCKSampleRate 0x8 /* 0: 44 MHz, 1: 88MHz */
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#define bRegulator0Standby 0x1
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#define bRegulatorPLLStandby 0x2
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#define bRegulator1Standby 0x4
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#define bPLLPowerUp 0x8
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#define bDPLLPowerUp 0x10
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#define bDA10PowerUp 0x20
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#define bAD7PowerUp 0x200
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#define bDA6PowerUp 0x2000
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#define bXtalPowerUp 0x4000
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#define b40MDClkPowerUP 0x8000
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#define bDA6DebugMode 0x20000
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#define bDA6Swing 0x380000
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#define bADClkPhase 0x4000000
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#define b80MClkDelay 0x18000000
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#define bAFEWatchDogEnable 0x20000000
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#define bXtalCap 0x0f000000
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#define bXtalCap01 0xc0000000
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#define bXtalCap23 0x3
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#define bXtalCap92x 0x0f000000
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#define bIntDifClkEnable 0x400
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#define bExtSigClkEnable 0x800
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#define bBandgapMbiasPowerUp 0x10000
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#define bAD11SHGain 0xc0000
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#define bAD11InputRange 0x700000
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#define bAD11OPCurrent 0x3800000
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#define bIPathLoopback 0x4000000
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#define bQPathLoopback 0x8000000
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#define bAFELoopback 0x10000000
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#define bDA10Swing 0x7e0
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#define bDA10Reverse 0x800
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#define bDAClkSource 0x1000
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#define bAD7InputRange 0x6000
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#define bAD7Gain 0x38000
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#define bAD7OutputCMMode 0x40000
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#define bAD7InputCMMode 0x380000
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#define bAD7Current 0xc00000
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#define bRegulatorAdjust 0x7000000
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#define bAD11PowerUpAtTx 0x1
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#define bDA10PSAtTx 0x10
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#define bAD11PowerUpAtRx 0x100
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#define bDA10PSAtRx 0x1000
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#define bCCKRxAGCFormat 0x200
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#define bPSDFFTSamplepPoint 0xc000
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#define bPSDAverageNum 0x3000
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#define bIQPathControl 0xc00
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#define bPSDFreq 0x3ff
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#define bPSDAntennaPath 0x30
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#define bPSDIQSwitch 0x40
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#define bPSDRxTrigger 0x400000
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#define bPSDTxTrigger 0x80000000
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#define bPSDSineToneScale 0x7f000000
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#define bPSDReport 0xffff
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/* Page 8 */
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#define bOFDMTxSC 0x30000000
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#define bCCKTxOn 0x1
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#define bOFDMTxOn 0x2
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/* Reset debug page and also HWord, LWord */
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#define bDebugPage 0xfff
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/* Reset debug page and LWord */
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#define bDebugItem 0xff
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#define bAntL 0x10
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#define bAntNonHT 0x100
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#define bAntHT1 0x1000
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#define bAntHT2 0x10000
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#define bAntHT1S1 0x100000
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#define bAntNonHTS1 0x1000000
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/* Page a */
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#define bCCKBBMode 0x3
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#define bCCKTxPowerSaving 0x80
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#define bCCKRxPowerSaving 0x40
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#define bCCKSideBand 0x10
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#define bCCKScramble 0x8
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#define bCCKAntDiversity 0x8000
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#define bCCKCarrierRecovery 0x4000
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#define bCCKTxRate 0x3000
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#define bCCKDCCancel 0x0800
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#define bCCKISICancel 0x0400
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#define bCCKMatchFilter 0x0200
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#define bCCKEqualizer 0x0100
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#define bCCKPreambleDetect 0x800000
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#define bCCKFastFalseCCA 0x400000
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#define bCCKChEstStart 0x300000
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#define bCCKCCACount 0x080000
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#define bCCKcs_lim 0x070000
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#define bCCKBistMode 0x80000000
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#define bCCKCCAMask 0x40000000
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#define bCCKTxDACPhase 0x4
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#define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
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#define bCCKr_cp_mode0 0x0100
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#define bCCKTxDCOffset 0xf0
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#define bCCKRxDCOffset 0xf
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#define bCCKCCAMode 0xc000
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#define bCCKFalseCS_lim 0x3f00
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#define bCCKCS_ratio 0xc00000
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#define bCCKCorgBit_sel 0x300000
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#define bCCKPD_lim 0x0f0000
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#define bCCKNewCCA 0x80000000
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#define bCCKRxHPofIG 0x8000
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#define bCCKRxIG 0x7f00
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#define bCCKLNAPolarity 0x800000
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#define bCCKRx1stGain 0x7f0000
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/* CCK Rx Initial gain polarity */
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#define bCCKRFExtend 0x20000000
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#define bCCKRxAGCSatLevel 0x1f000000
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#define bCCKRxAGCSatCount 0xe0
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/* AGCSAmp_dly */
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#define bCCKRxRFSettle 0x1f
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#define bCCKFixedRxAGC 0x8000
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/*#define bCCKRxAGCFormat 0x4000 remove to HSSI register 0x824 */
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#define bCCKAntennaPolarity 0x2000
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#define bCCKTxFilterType 0x0c00
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#define bCCKRxAGCReportType 0x0300
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#define bCCKRxDAGCEn 0x80000000
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#define bCCKRxDAGCPeriod 0x20000000
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#define bCCKRxDAGCSatLevel 0x1f000000
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#define bCCKTimingRecovery 0x800000
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#define bCCKTxC0 0x3f0000
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#define bCCKTxC1 0x3f000000
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#define bCCKTxC2 0x3f
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#define bCCKTxC3 0x3f00
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#define bCCKTxC4 0x3f0000
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#define bCCKTxC5 0x3f000000
|
#define bCCKTxC6 0x3f
|
#define bCCKTxC7 0x3f00
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#define bCCKDebugPort 0xff0000
|
#define bCCKDACDebug 0x0f000000
|
#define bCCKFalseAlarmEnable 0x8000
|
#define bCCKFalseAlarmRead 0x4000
|
#define bCCKTRSSI 0x7f
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#define bCCKRxAGCReport 0xfe
|
#define bCCKRxReport_AntSel 0x80000000
|
#define bCCKRxReport_MFOff 0x40000000
|
#define bCCKRxRxReport_SQLoss 0x20000000
|
#define bCCKRxReport_Pktloss 0x10000000
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#define bCCKRxReport_Lockedbit 0x08000000
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#define bCCKRxReport_RateError 0x04000000
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#define bCCKRxReport_RxRate 0x03000000
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#define bCCKRxFACounterLower 0xff
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#define bCCKRxFACounterUpper 0xff000000
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#define bCCKRxHPAGCStart 0xe000
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#define bCCKRxHPAGCFinal 0x1c00
|
|
#define bCCKRxFalseAlarmEnable 0x8000
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#define bCCKFACounterFreeze 0x4000
|
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#define bCCKTxPathSel 0x10000000
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#define bCCKDefaultRxPath 0xc000000
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#define bCCKOptionRxPath 0x3000000
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/* Page c */
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#define bNumOfSTF 0x3
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#define bShift_L 0xc0
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#define bGI_TH 0xc
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#define bRxPathA 0x1
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#define bRxPathB 0x2
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#define bRxPathC 0x4
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#define bRxPathD 0x8
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#define bTxPathA 0x1
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#define bTxPathB 0x2
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#define bTxPathC 0x4
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#define bTxPathD 0x8
|
#define bTRSSIFreq 0x200
|
#define bADCBackoff 0x3000
|
#define bDFIRBackoff 0xc000
|
#define bTRSSILatchPhase 0x10000
|
#define bRxIDCOffset 0xff
|
#define bRxQDCOffset 0xff00
|
#define bRxDFIRMode 0x1800000
|
#define bRxDCNFType 0xe000000
|
#define bRXIQImb_A 0x3ff
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#define bRXIQImb_B 0xfc00
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#define bRXIQImb_C 0x3f0000
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#define bRXIQImb_D 0xffc00000
|
#define bDC_dc_Notch 0x60000
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#define bRxNBINotch 0x1f000000
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#define bPD_TH 0xf
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#define bPD_TH_Opt2 0xc000
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#define bPWED_TH 0x700
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#define bIfMF_Win_L 0x800
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#define bPD_Option 0x1000
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#define bMF_Win_L 0xe000
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#define bBW_Search_L 0x30000
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#define bwin_enh_L 0xc0000
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#define bBW_TH 0x700000
|
#define bED_TH2 0x3800000
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#define bBW_option 0x4000000
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#define bRatio_TH 0x18000000
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#define bWindow_L 0xe0000000
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#define bSBD_Option 0x1
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#define bFrame_TH 0x1c
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#define bFS_Option 0x60
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#define bDC_Slope_check 0x80
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#define bFGuard_Counter_DC_L 0xe00
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#define bFrame_Weight_Short 0x7000
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#define bSub_Tune 0xe00000
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#define bFrame_DC_Length 0xe000000
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#define bSBD_start_offset 0x30000000
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#define bFrame_TH_2 0x7
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#define bFrame_GI2_TH 0x38
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#define bGI2_Sync_en 0x40
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#define bSarch_Short_Early 0x300
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#define bSarch_Short_Late 0xc00
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#define bSarch_GI2_Late 0x70000
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#define bCFOAntSum 0x1
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#define bCFOAcc 0x2
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#define bCFOStartOffset 0xc
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#define bCFOLookBack 0x70
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#define bCFOSumWeight 0x80
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#define bDAGCEnable 0x10000
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#define bTXIQImb_A 0x3ff
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#define bTXIQImb_B 0xfc00
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#define bTXIQImb_C 0x3f0000
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#define bTXIQImb_D 0xffc00000
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#define bTxIDCOffset 0xff
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#define bTxQDCOffset 0xff00
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#define bTxDFIRMode 0x10000
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#define bTxPesudoNoiseOn 0x4000000
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#define bTxPesudoNoise_A 0xff
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#define bTxPesudoNoise_B 0xff00
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#define bTxPesudoNoise_C 0xff0000
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#define bTxPesudoNoise_D 0xff000000
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#define bCCADropOption 0x20000
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#define bCCADropThres 0xfff00000
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#define bEDCCA_H 0xf
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#define bEDCCA_L 0xf0
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#define bLambda_ED 0x300
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#define bRxInitialGain 0x7f
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#define bRxAntDivEn 0x80
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#define bRxAGCAddressForLNA 0x7f00
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#define bRxHighPowerFlow 0x8000
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#define bRxAGCFreezeThres 0xc0000
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#define bRxFreezeStep_AGC1 0x300000
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#define bRxFreezeStep_AGC2 0xc00000
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#define bRxFreezeStep_AGC3 0x3000000
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#define bRxFreezeStep_AGC0 0xc000000
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#define bRxRssi_Cmp_En 0x10000000
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#define bRxQuickAGCEn 0x20000000
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#define bRxAGCFreezeThresMode 0x40000000
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#define bRxOverFlowCheckType 0x80000000
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#define bRxAGCShift 0x7f
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#define bTRSW_Tri_Only 0x80
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#define bPowerThres 0x300
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#define bRxAGCEn 0x1
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#define bRxAGCTogetherEn 0x2
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#define bRxAGCMin 0x4
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#define bRxHP_Ini 0x7
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#define bRxHP_TRLNA 0x70
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#define bRxHP_RSSI 0x700
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#define bRxHP_BBP1 0x7000
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#define bRxHP_BBP2 0x70000
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#define bRxHP_BBP3 0x700000
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/* The threshold for high power */
|
#define bRSSI_H 0x7f0000
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/* The threshold for ant diversity */
|
#define bRSSI_Gen 0x7f000000
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#define bRxSettle_TRSW 0x7
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#define bRxSettle_LNA 0x38
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#define bRxSettle_RSSI 0x1c0
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#define bRxSettle_BBP 0xe00
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#define bRxSettle_RxHP 0x7000
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#define bRxSettle_AntSW_RSSI 0x38000
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#define bRxSettle_AntSW 0xc0000
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#define bRxProcessTime_DAGC 0x300000
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#define bRxSettle_HSSI 0x400000
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#define bRxProcessTime_BBPPW 0x800000
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#define bRxAntennaPowerShift 0x3000000
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#define bRSSITableSelect 0xc000000
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#define bRxHP_Final 0x7000000
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#define bRxHTSettle_BBP 0x7
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#define bRxHTSettle_HSSI 0x8
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#define bRxHTSettle_RxHP 0x70
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#define bRxHTSettle_BBPPW 0x80
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#define bRxHTSettle_Idle 0x300
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#define bRxHTSettle_Reserved 0x1c00
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#define bRxHTRxHPEn 0x8000
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#define bRxHTAGCFreezeThres 0x30000
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#define bRxHTAGCTogetherEn 0x40000
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#define bRxHTAGCMin 0x80000
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#define bRxHTAGCEn 0x100000
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#define bRxHTDAGCEn 0x200000
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#define bRxHTRxHP_BBP 0x1c00000
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#define bRxHTRxHP_Final 0xe0000000
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#define bRxPWRatioTH 0x3
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#define bRxPWRatioEn 0x4
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#define bRxMFHold 0x3800
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#define bRxPD_Delay_TH1 0x38
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#define bRxPD_Delay_TH2 0x1c0
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#define bRxPD_DC_COUNT_MAX 0x600
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/*#define bRxMF_Hold 0x3800*/
|
#define bRxPD_Delay_TH 0x8000
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#define bRxProcess_Delay 0xf0000
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#define bRxSearchrange_GI2_Early 0x700000
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#define bRxFrame_Guard_Counter_L 0x3800000
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#define bRxSGI_Guard_L 0xc000000
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#define bRxSGI_Search_L 0x30000000
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#define bRxSGI_TH 0xc0000000
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#define bDFSCnt0 0xff
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#define bDFSCnt1 0xff00
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#define bDFSFlag 0xf0000
|
|
#define bMFWeightSum 0x300000
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#define bMinIdxTH 0x7f000000
|
|
#define bDAFormat 0x40000
|
|
#define bTxChEmuEnable 0x01000000
|
|
#define bTRSWIsolation_A 0x7f
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#define bTRSWIsolation_B 0x7f00
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#define bTRSWIsolation_C 0x7f0000
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#define bTRSWIsolation_D 0x7f000000
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|
#define bExtLNAGain 0x7c00
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|
/* Page d */
|
#define bSTBCEn 0x4
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#define bAntennaMapping 0x10
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#define bNss 0x20
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#define bCFOAntSumD 0x200
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#define bPHYCounterReset 0x8000000
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#define bCFOReportGet 0x4000000
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#define bOFDMContinueTx 0x10000000
|
#define bOFDMSingleCarrier 0x20000000
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#define bOFDMSingleTone 0x40000000
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/* #define bRxPath1 0x01
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* #define bRxPath2 0x02
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* #define bRxPath3 0x04
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* #define bRxPath4 0x08
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* #define bTxPath1 0x10
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* #define bTxPath2 0x20
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*/
|
#define bHTDetect 0x100
|
#define bCFOEn 0x10000
|
#define bCFOValue 0xfff00000
|
#define bSigTone_Re 0x3f
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#define bSigTone_Im 0x7f00
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#define bCounter_CCA 0xffff
|
#define bCounter_ParityFail 0xffff0000
|
#define bCounter_RateIllegal 0xffff
|
#define bCounter_CRC8Fail 0xffff0000
|
#define bCounter_MCSNoSupport 0xffff
|
#define bCounter_FastSync 0xffff
|
#define bShortCFO 0xfff
|
#define bShortCFOTLength 12 /* total */
|
#define bShortCFOFLength 11 /* fraction */
|
#define bLongCFO 0x7ff
|
#define bLongCFOTLength 11
|
#define bLongCFOFLength 11
|
#define bTailCFO 0x1fff
|
#define bTailCFOTLength 13
|
#define bTailCFOFLength 12
|
|
#define bmax_en_pwdB 0xffff
|
#define bCC_power_dB 0xffff0000
|
#define bnoise_pwdB 0xffff
|
#define bPowerMeasTLength 10
|
#define bPowerMeasFLength 3
|
#define bRx_HT_BW 0x1
|
#define bRxSC 0x6
|
#define bRx_HT 0x8
|
|
#define bNB_intf_det_on 0x1
|
#define bIntf_win_len_cfg 0x30
|
#define bNB_Intf_TH_cfg 0x1c0
|
|
#define bRFGain 0x3f
|
#define bTableSel 0x40
|
#define bTRSW 0x80
|
|
#define bRxSNR_A 0xff
|
#define bRxSNR_B 0xff00
|
#define bRxSNR_C 0xff0000
|
#define bRxSNR_D 0xff000000
|
#define bSNREVMTLength 8
|
#define bSNREVMFLength 1
|
|
#define bCSI1st 0xff
|
#define bCSI2nd 0xff00
|
#define bRxEVM1st 0xff0000
|
#define bRxEVM2nd 0xff000000
|
|
#define bSIGEVM 0xff
|
#define bPWDB 0xff00
|
#define bSGIEN 0x10000
|
|
#define bSFactorQAM1 0xf
|
#define bSFactorQAM2 0xf0
|
#define bSFactorQAM3 0xf00
|
#define bSFactorQAM4 0xf000
|
#define bSFactorQAM5 0xf0000
|
#define bSFactorQAM6 0xf0000
|
#define bSFactorQAM7 0xf00000
|
#define bSFactorQAM8 0xf000000
|
#define bSFactorQAM9 0xf0000000
|
#define bCSIScheme 0x100000
|
|
#define bNoiseLvlTopSet 0x3
|
#define bChSmooth 0x4
|
#define bChSmoothCfg1 0x38
|
#define bChSmoothCfg2 0x1c0
|
#define bChSmoothCfg3 0xe00
|
#define bChSmoothCfg4 0x7000
|
#define bMRCMode 0x800000
|
#define bTHEVMCfg 0x7000000
|
|
#define bLoopFitType 0x1
|
#define bUpdCFO 0x40
|
#define bUpdCFOOffData 0x80
|
#define bAdvUpdCFO 0x100
|
#define bAdvTimeCtrl 0x800
|
#define bUpdClko 0x1000
|
#define bFC 0x6000
|
#define bTrackingMode 0x8000
|
#define bPhCmpEnable 0x10000
|
#define bUpdClkoLTF 0x20000
|
#define bComChCFO 0x40000
|
#define bCSIEstiMode 0x80000
|
#define bAdvUpdEqz 0x100000
|
#define bUChCfg 0x7000000
|
#define bUpdEqz 0x8000000
|
|
/* Page e */
|
#define bTxAGCRate18_06 0x7f7f7f7f
|
#define bTxAGCRate54_24 0x7f7f7f7f
|
#define bTxAGCRateMCS32 0x7f
|
#define bTxAGCRateCCK 0x7f00
|
#define bTxAGCRateMCS3_MCS0 0x7f7f7f7f
|
#define bTxAGCRateMCS7_MCS4 0x7f7f7f7f
|
#define bTxAGCRateMCS11_MCS8 0x7f7f7f7f
|
#define bTxAGCRateMCS15_MCS12 0x7f7f7f7f
|
|
#define bRxPesudoNoiseOn 0x20000000 /* Rx Pseduo noise */
|
#define bRxPesudoNoise_A 0xff
|
#define bRxPesudoNoise_B 0xff00
|
#define bRxPesudoNoise_C 0xff0000
|
#define bRxPesudoNoise_D 0xff000000
|
#define bPesudoNoiseState_A 0xffff
|
#define bPesudoNoiseState_B 0xffff0000
|
#define bPesudoNoiseState_C 0xffff
|
#define bPesudoNoiseState_D 0xffff0000
|
|
/* RF Zebra 1 */
|
#define bZebra1_HSSIEnable 0x8
|
#define bZebra1_TRxControl 0xc00
|
#define bZebra1_TRxGainSetting 0x07f
|
#define bZebra1_RxCorner 0xc00
|
#define bZebra1_TxChargePump 0x38
|
#define bZebra1_RxChargePump 0x7
|
#define bZebra1_ChannelNum 0xf80
|
#define bZebra1_TxLPFBW 0x400
|
#define bZebra1_RxLPFBW 0x600
|
|
/* Zebra4 */
|
#define bRTL8256RegModeCtrl1 0x100
|
#define bRTL8256RegModeCtrl0 0x40
|
#define bRTL8256_TxLPFBW 0x18
|
#define bRTL8256_RxLPFBW 0x600
|
|
/* RTL8258 */
|
#define bRTL8258_TxLPFBW 0xc
|
#define bRTL8258_RxLPFBW 0xc00
|
#define bRTL8258_RSSILPFBW 0xc0
|
|
/* byte enable for sb_write */
|
#define bByte0 0x1
|
#define bByte1 0x2
|
#define bByte2 0x4
|
#define bByte3 0x8
|
#define bWord0 0x3
|
#define bWord1 0xc
|
#define bDWord 0xf
|
|
/* for PutRegsetting & GetRegSetting BitMask */
|
#define bMaskByte0 0xff
|
#define bMaskByte1 0xff00
|
#define bMaskByte2 0xff0000
|
#define bMaskByte3 0xff000000
|
#define bMaskHWord 0xffff0000
|
#define bMaskLWord 0x0000ffff
|
#define bMaskDWord 0xffffffff
|
|
/* for PutRFRegsetting & GetRFRegSetting BitMask */
|
#define bMask12Bits 0xfff
|
|
#define bEnable 0x1
|
#define bDisable 0x0
|
|
#define LeftAntenna 0x0
|
#define RightAntenna 0x1
|
|
#define tCheckTxStatus 500 /* 500 ms */
|
#define tUpdateRxCounter 100 /* 100 ms */
|
|
#define rateCCK 0
|
#define rateOFDM 1
|
#define rateHT 2
|
|
#define bPMAC_End 0x1ff /* define Register-End */
|
#define bFPGAPHY0_End 0x8ff
|
#define bFPGAPHY1_End 0x9ff
|
#define bCCKPHY0_End 0xaff
|
#define bOFDMPHY0_End 0xcff
|
#define bOFDMPHY1_End 0xdff
|
|
|
#define bPMACControl 0x0
|
#define bWMACControl 0x1
|
#define bWNICControl 0x2
|
|
#define PathA 0x0
|
#define PathB 0x1
|
#define PathC 0x2
|
#define PathD 0x3
|
|
#define rRTL8256RxMixerPole 0xb
|
#define bZebraRxMixerPole 0x6
|
#define rRTL8256TxBBOPBias 0x9
|
#define bRTL8256TxBBOPBias 0x400
|
#define rRTL8256TxBBBW 19
|
#define bRTL8256TxBBBW 0x18
|
|
#endif
|
