/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef ASIC_REG_TPC3_CFG_REGS_H_
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#define ASIC_REG_TPC3_CFG_REGS_H_
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/*
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*****************************************
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* TPC3_CFG (Prototype: TPC)
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*****************************************
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*/
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#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW 0xEC6400
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#define mmTPC3_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH 0xEC6404
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#define mmTPC3_CFG_KERNEL_TENSOR_0_PADDING_VALUE 0xEC6408
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#define mmTPC3_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG 0xEC640C
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_SIZE 0xEC6410
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE 0xEC6414
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_SIZE 0xEC6418
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE 0xEC641C
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_SIZE 0xEC6420
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE 0xEC6424
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_SIZE 0xEC6428
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE 0xEC642C
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_SIZE 0xEC6430
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#define mmTPC3_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE 0xEC6434
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#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_LOW 0xEC6438
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#define mmTPC3_CFG_KERNEL_TENSOR_1_BASE_ADDR_HIGH 0xEC643C
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#define mmTPC3_CFG_KERNEL_TENSOR_1_PADDING_VALUE 0xEC6440
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#define mmTPC3_CFG_KERNEL_TENSOR_1_TENSOR_CONFIG 0xEC6444
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_SIZE 0xEC6448
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_0_STRIDE 0xEC644C
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_SIZE 0xEC6450
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_1_STRIDE 0xEC6454
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_SIZE 0xEC6458
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_2_STRIDE 0xEC645C
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_SIZE 0xEC6460
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_3_STRIDE 0xEC6464
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_SIZE 0xEC6468
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#define mmTPC3_CFG_KERNEL_TENSOR_1_DIM_4_STRIDE 0xEC646C
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#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_LOW 0xEC6470
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#define mmTPC3_CFG_KERNEL_TENSOR_2_BASE_ADDR_HIGH 0xEC6474
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#define mmTPC3_CFG_KERNEL_TENSOR_2_PADDING_VALUE 0xEC6478
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#define mmTPC3_CFG_KERNEL_TENSOR_2_TENSOR_CONFIG 0xEC647C
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_SIZE 0xEC6480
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_0_STRIDE 0xEC6484
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_SIZE 0xEC6488
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_1_STRIDE 0xEC648C
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_SIZE 0xEC6490
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_2_STRIDE 0xEC6494
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_SIZE 0xEC6498
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_3_STRIDE 0xEC649C
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_SIZE 0xEC64A0
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#define mmTPC3_CFG_KERNEL_TENSOR_2_DIM_4_STRIDE 0xEC64A4
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#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_LOW 0xEC64A8
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#define mmTPC3_CFG_KERNEL_TENSOR_3_BASE_ADDR_HIGH 0xEC64AC
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#define mmTPC3_CFG_KERNEL_TENSOR_3_PADDING_VALUE 0xEC64B0
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#define mmTPC3_CFG_KERNEL_TENSOR_3_TENSOR_CONFIG 0xEC64B4
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_SIZE 0xEC64B8
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_0_STRIDE 0xEC64BC
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_SIZE 0xEC64C0
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_1_STRIDE 0xEC64C4
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_SIZE 0xEC64C8
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_2_STRIDE 0xEC64CC
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_SIZE 0xEC64D0
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_3_STRIDE 0xEC64D4
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_SIZE 0xEC64D8
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#define mmTPC3_CFG_KERNEL_TENSOR_3_DIM_4_STRIDE 0xEC64DC
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#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_LOW 0xEC64E0
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#define mmTPC3_CFG_KERNEL_TENSOR_4_BASE_ADDR_HIGH 0xEC64E4
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#define mmTPC3_CFG_KERNEL_TENSOR_4_PADDING_VALUE 0xEC64E8
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#define mmTPC3_CFG_KERNEL_TENSOR_4_TENSOR_CONFIG 0xEC64EC
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_SIZE 0xEC64F0
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_0_STRIDE 0xEC64F4
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_SIZE 0xEC64F8
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_1_STRIDE 0xEC64FC
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_SIZE 0xEC6500
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_2_STRIDE 0xEC6504
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_SIZE 0xEC6508
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_3_STRIDE 0xEC650C
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_SIZE 0xEC6510
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#define mmTPC3_CFG_KERNEL_TENSOR_4_DIM_4_STRIDE 0xEC6514
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#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_LOW 0xEC6518
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#define mmTPC3_CFG_KERNEL_TENSOR_5_BASE_ADDR_HIGH 0xEC651C
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#define mmTPC3_CFG_KERNEL_TENSOR_5_PADDING_VALUE 0xEC6520
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#define mmTPC3_CFG_KERNEL_TENSOR_5_TENSOR_CONFIG 0xEC6524
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_SIZE 0xEC6528
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_0_STRIDE 0xEC652C
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_SIZE 0xEC6530
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_1_STRIDE 0xEC6534
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_SIZE 0xEC6538
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_2_STRIDE 0xEC653C
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_SIZE 0xEC6540
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_3_STRIDE 0xEC6544
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_SIZE 0xEC6548
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#define mmTPC3_CFG_KERNEL_TENSOR_5_DIM_4_STRIDE 0xEC654C
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#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_LOW 0xEC6550
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#define mmTPC3_CFG_KERNEL_TENSOR_6_BASE_ADDR_HIGH 0xEC6554
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#define mmTPC3_CFG_KERNEL_TENSOR_6_PADDING_VALUE 0xEC6558
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#define mmTPC3_CFG_KERNEL_TENSOR_6_TENSOR_CONFIG 0xEC655C
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_SIZE 0xEC6560
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_0_STRIDE 0xEC6564
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_SIZE 0xEC6568
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_1_STRIDE 0xEC656C
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_SIZE 0xEC6570
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_2_STRIDE 0xEC6574
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_SIZE 0xEC6578
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_3_STRIDE 0xEC657C
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_SIZE 0xEC6580
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#define mmTPC3_CFG_KERNEL_TENSOR_6_DIM_4_STRIDE 0xEC6584
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#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_LOW 0xEC6588
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#define mmTPC3_CFG_KERNEL_TENSOR_7_BASE_ADDR_HIGH 0xEC658C
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#define mmTPC3_CFG_KERNEL_TENSOR_7_PADDING_VALUE 0xEC6590
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#define mmTPC3_CFG_KERNEL_TENSOR_7_TENSOR_CONFIG 0xEC6594
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_SIZE 0xEC6598
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_0_STRIDE 0xEC659C
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_SIZE 0xEC65A0
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_1_STRIDE 0xEC65A4
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_SIZE 0xEC65A8
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_2_STRIDE 0xEC65AC
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_SIZE 0xEC65B0
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_3_STRIDE 0xEC65B4
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_SIZE 0xEC65B8
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#define mmTPC3_CFG_KERNEL_TENSOR_7_DIM_4_STRIDE 0xEC65BC
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#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_LOW 0xEC65C0
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#define mmTPC3_CFG_KERNEL_TENSOR_8_BASE_ADDR_HIGH 0xEC65C4
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#define mmTPC3_CFG_KERNEL_TENSOR_8_PADDING_VALUE 0xEC65C8
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#define mmTPC3_CFG_KERNEL_TENSOR_8_TENSOR_CONFIG 0xEC65CC
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_SIZE 0xEC65D0
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_0_STRIDE 0xEC65D4
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_SIZE 0xEC65D8
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_1_STRIDE 0xEC65DC
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_SIZE 0xEC65E0
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_2_STRIDE 0xEC65E4
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_SIZE 0xEC65E8
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_3_STRIDE 0xEC65EC
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_SIZE 0xEC65F0
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#define mmTPC3_CFG_KERNEL_TENSOR_8_DIM_4_STRIDE 0xEC65F4
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#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_LOW 0xEC65F8
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#define mmTPC3_CFG_KERNEL_TENSOR_9_BASE_ADDR_HIGH 0xEC65FC
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#define mmTPC3_CFG_KERNEL_TENSOR_9_PADDING_VALUE 0xEC6600
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#define mmTPC3_CFG_KERNEL_TENSOR_9_TENSOR_CONFIG 0xEC6604
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_SIZE 0xEC6608
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_0_STRIDE 0xEC660C
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_SIZE 0xEC6610
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_1_STRIDE 0xEC6614
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_SIZE 0xEC6618
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_2_STRIDE 0xEC661C
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_SIZE 0xEC6620
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_3_STRIDE 0xEC6624
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_SIZE 0xEC6628
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#define mmTPC3_CFG_KERNEL_TENSOR_9_DIM_4_STRIDE 0xEC662C
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#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_LOW 0xEC6630
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#define mmTPC3_CFG_KERNEL_TENSOR_10_BASE_ADDR_HIGH 0xEC6634
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#define mmTPC3_CFG_KERNEL_TENSOR_10_PADDING_VALUE 0xEC6638
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#define mmTPC3_CFG_KERNEL_TENSOR_10_TENSOR_CONFIG 0xEC663C
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_SIZE 0xEC6640
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_0_STRIDE 0xEC6644
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_SIZE 0xEC6648
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_1_STRIDE 0xEC664C
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_SIZE 0xEC6650
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_2_STRIDE 0xEC6654
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_SIZE 0xEC6658
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_3_STRIDE 0xEC665C
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_SIZE 0xEC6660
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#define mmTPC3_CFG_KERNEL_TENSOR_10_DIM_4_STRIDE 0xEC6664
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#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_LOW 0xEC6668
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#define mmTPC3_CFG_KERNEL_TENSOR_11_BASE_ADDR_HIGH 0xEC666C
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#define mmTPC3_CFG_KERNEL_TENSOR_11_PADDING_VALUE 0xEC6670
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#define mmTPC3_CFG_KERNEL_TENSOR_11_TENSOR_CONFIG 0xEC6674
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_SIZE 0xEC6678
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_0_STRIDE 0xEC667C
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_SIZE 0xEC6680
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_1_STRIDE 0xEC6684
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_SIZE 0xEC6688
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_2_STRIDE 0xEC668C
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_SIZE 0xEC6690
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_3_STRIDE 0xEC6694
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_SIZE 0xEC6698
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#define mmTPC3_CFG_KERNEL_TENSOR_11_DIM_4_STRIDE 0xEC669C
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#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_LOW 0xEC66A0
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#define mmTPC3_CFG_KERNEL_TENSOR_12_BASE_ADDR_HIGH 0xEC66A4
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#define mmTPC3_CFG_KERNEL_TENSOR_12_PADDING_VALUE 0xEC66A8
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#define mmTPC3_CFG_KERNEL_TENSOR_12_TENSOR_CONFIG 0xEC66AC
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_SIZE 0xEC66B0
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_0_STRIDE 0xEC66B4
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_SIZE 0xEC66B8
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_1_STRIDE 0xEC66BC
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_SIZE 0xEC66C0
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_2_STRIDE 0xEC66C4
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_SIZE 0xEC66C8
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_3_STRIDE 0xEC66CC
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_SIZE 0xEC66D0
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#define mmTPC3_CFG_KERNEL_TENSOR_12_DIM_4_STRIDE 0xEC66D4
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#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_LOW 0xEC66D8
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#define mmTPC3_CFG_KERNEL_TENSOR_13_BASE_ADDR_HIGH 0xEC66DC
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#define mmTPC3_CFG_KERNEL_TENSOR_13_PADDING_VALUE 0xEC66E0
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#define mmTPC3_CFG_KERNEL_TENSOR_13_TENSOR_CONFIG 0xEC66E4
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_SIZE 0xEC66E8
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_0_STRIDE 0xEC66EC
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_SIZE 0xEC66F0
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_1_STRIDE 0xEC66F4
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_SIZE 0xEC66F8
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_2_STRIDE 0xEC66FC
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_SIZE 0xEC6700
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_3_STRIDE 0xEC6704
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_SIZE 0xEC6708
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#define mmTPC3_CFG_KERNEL_TENSOR_13_DIM_4_STRIDE 0xEC670C
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#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_LOW 0xEC6710
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#define mmTPC3_CFG_KERNEL_TENSOR_14_BASE_ADDR_HIGH 0xEC6714
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#define mmTPC3_CFG_KERNEL_TENSOR_14_PADDING_VALUE 0xEC6718
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#define mmTPC3_CFG_KERNEL_TENSOR_14_TENSOR_CONFIG 0xEC671C
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_SIZE 0xEC6720
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_0_STRIDE 0xEC6724
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_SIZE 0xEC6728
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_1_STRIDE 0xEC672C
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_SIZE 0xEC6730
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_2_STRIDE 0xEC6734
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_SIZE 0xEC6738
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_3_STRIDE 0xEC673C
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_SIZE 0xEC6740
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#define mmTPC3_CFG_KERNEL_TENSOR_14_DIM_4_STRIDE 0xEC6744
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#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_LOW 0xEC6748
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#define mmTPC3_CFG_KERNEL_TENSOR_15_BASE_ADDR_HIGH 0xEC674C
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#define mmTPC3_CFG_KERNEL_TENSOR_15_PADDING_VALUE 0xEC6750
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#define mmTPC3_CFG_KERNEL_TENSOR_15_TENSOR_CONFIG 0xEC6754
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_SIZE 0xEC6758
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_0_STRIDE 0xEC675C
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_SIZE 0xEC6760
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_1_STRIDE 0xEC6764
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_SIZE 0xEC6768
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_2_STRIDE 0xEC676C
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_SIZE 0xEC6770
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_3_STRIDE 0xEC6774
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_SIZE 0xEC6778
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#define mmTPC3_CFG_KERNEL_TENSOR_15_DIM_4_STRIDE 0xEC677C
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#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_MESSAGE 0xEC6780
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#define mmTPC3_CFG_KERNEL_SYNC_OBJECT_ADDR 0xEC6784
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#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_LOW 0xEC6788
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#define mmTPC3_CFG_KERNEL_KERNEL_BASE_ADDRESS_HIGH 0xEC678C
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#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_0 0xEC6790
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#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_0 0xEC6794
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#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_1 0xEC6798
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#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_1 0xEC679C
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#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_2 0xEC67A0
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#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_2 0xEC67A4
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#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_3 0xEC67A8
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#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_3 0xEC67AC
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#define mmTPC3_CFG_KERNEL_TID_BASE_DIM_4 0xEC67B0
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#define mmTPC3_CFG_KERNEL_TID_SIZE_DIM_4 0xEC67B4
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#define mmTPC3_CFG_KERNEL_KERNEL_CONFIG 0xEC67B8
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#define mmTPC3_CFG_KERNEL_KERNEL_ID 0xEC67BC
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#define mmTPC3_CFG_KERNEL_SRF_0 0xEC67C0
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#define mmTPC3_CFG_KERNEL_SRF_1 0xEC67C4
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#define mmTPC3_CFG_KERNEL_SRF_2 0xEC67C8
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#define mmTPC3_CFG_KERNEL_SRF_3 0xEC67CC
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#define mmTPC3_CFG_KERNEL_SRF_4 0xEC67D0
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#define mmTPC3_CFG_KERNEL_SRF_5 0xEC67D4
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#define mmTPC3_CFG_KERNEL_SRF_6 0xEC67D8
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#define mmTPC3_CFG_KERNEL_SRF_7 0xEC67DC
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#define mmTPC3_CFG_KERNEL_SRF_8 0xEC67E0
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#define mmTPC3_CFG_KERNEL_SRF_9 0xEC67E4
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#define mmTPC3_CFG_KERNEL_SRF_10 0xEC67E8
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#define mmTPC3_CFG_KERNEL_SRF_11 0xEC67EC
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#define mmTPC3_CFG_KERNEL_SRF_12 0xEC67F0
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#define mmTPC3_CFG_KERNEL_SRF_13 0xEC67F4
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#define mmTPC3_CFG_KERNEL_SRF_14 0xEC67F8
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#define mmTPC3_CFG_KERNEL_SRF_15 0xEC67FC
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#define mmTPC3_CFG_KERNEL_SRF_16 0xEC6800
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#define mmTPC3_CFG_KERNEL_SRF_17 0xEC6804
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#define mmTPC3_CFG_KERNEL_SRF_18 0xEC6808
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#define mmTPC3_CFG_KERNEL_SRF_19 0xEC680C
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#define mmTPC3_CFG_KERNEL_SRF_20 0xEC6810
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#define mmTPC3_CFG_KERNEL_SRF_21 0xEC6814
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#define mmTPC3_CFG_KERNEL_SRF_22 0xEC6818
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#define mmTPC3_CFG_KERNEL_SRF_23 0xEC681C
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#define mmTPC3_CFG_KERNEL_SRF_24 0xEC6820
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#define mmTPC3_CFG_KERNEL_SRF_25 0xEC6824
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#define mmTPC3_CFG_KERNEL_SRF_26 0xEC6828
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#define mmTPC3_CFG_KERNEL_SRF_27 0xEC682C
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#define mmTPC3_CFG_KERNEL_SRF_28 0xEC6830
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|
#define mmTPC3_CFG_KERNEL_SRF_29 0xEC6834
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|
#define mmTPC3_CFG_KERNEL_SRF_30 0xEC6838
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|
#define mmTPC3_CFG_KERNEL_SRF_31 0xEC683C
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|
#define mmTPC3_CFG_ROUND_CSR 0xEC68FC
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#define mmTPC3_CFG_PROT 0xEC6900
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|
#define mmTPC3_CFG_SEMAPHORE 0xEC6908
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|
#define mmTPC3_CFG_VFLAGS 0xEC690C
|
|
#define mmTPC3_CFG_SFLAGS 0xEC6910
|
|
#define mmTPC3_CFG_LFSR_POLYNOM 0xEC6918
|
|
#define mmTPC3_CFG_STATUS 0xEC691C
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#define mmTPC3_CFG_CFG_BASE_ADDRESS_HIGH 0xEC6920
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|
#define mmTPC3_CFG_CFG_SUBTRACT_VALUE 0xEC6924
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#define mmTPC3_CFG_SM_BASE_ADDRESS_HIGH 0xEC692C
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#define mmTPC3_CFG_TPC_CMD 0xEC6930
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|
#define mmTPC3_CFG_TPC_EXECUTE 0xEC6938
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#define mmTPC3_CFG_TPC_STALL 0xEC693C
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#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_LOW 0xEC6940
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|
#define mmTPC3_CFG_ICACHE_BASE_ADDERESS_HIGH 0xEC6944
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#define mmTPC3_CFG_RD_RATE_LIMIT 0xEC6948
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#define mmTPC3_CFG_WR_RATE_LIMIT 0xEC6950
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#define mmTPC3_CFG_MSS_CONFIG 0xEC6954
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#define mmTPC3_CFG_TPC_INTR_CAUSE 0xEC6958
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|
#define mmTPC3_CFG_TPC_INTR_MASK 0xEC695C
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#define mmTPC3_CFG_WQ_CREDITS 0xEC6960
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|
#define mmTPC3_CFG_ARUSER_LO 0xEC6964
|
|
#define mmTPC3_CFG_ARUSER_HI 0xEC6968
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#define mmTPC3_CFG_AWUSER_LO 0xEC696C
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#define mmTPC3_CFG_AWUSER_HI 0xEC6970
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#define mmTPC3_CFG_OPCODE_EXEC 0xEC6974
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#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_LO 0xEC6978
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|
#define mmTPC3_CFG_LUT_FUNC32_BASE_ADDR_HI 0xEC697C
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|
#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_LO 0xEC6980
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|
#define mmTPC3_CFG_LUT_FUNC64_BASE_ADDR_HI 0xEC6984
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|
#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_LO 0xEC6988
|
|
#define mmTPC3_CFG_LUT_FUNC128_BASE_ADDR_HI 0xEC698C
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|
#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_LO 0xEC6990
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|
#define mmTPC3_CFG_LUT_FUNC256_BASE_ADDR_HI 0xEC6994
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|
#define mmTPC3_CFG_TSB_CFG_MAX_SIZE 0xEC6998
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|
#define mmTPC3_CFG_TSB_CFG 0xEC699C
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|
#define mmTPC3_CFG_DBGMEM_ADD 0xEC69A0
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|
#define mmTPC3_CFG_DBGMEM_DATA_WR 0xEC69A4
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|
#define mmTPC3_CFG_DBGMEM_DATA_RD 0xEC69A8
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|
#define mmTPC3_CFG_DBGMEM_CTRL 0xEC69AC
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#define mmTPC3_CFG_DBGMEM_RC 0xEC69B0
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#define mmTPC3_CFG_TSB_INFLIGHT_CNTR 0xEC69B4
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#define mmTPC3_CFG_WQ_INFLIGHT_CNTR 0xEC69B8
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|
#define mmTPC3_CFG_WQ_LBW_TOTAL_CNTR 0xEC69BC
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|
#define mmTPC3_CFG_WQ_HBW_TOTAL_CNTR 0xEC69C0
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|
#define mmTPC3_CFG_IRQ_OCCOUPY_CNTR 0xEC69C4
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#define mmTPC3_CFG_FUNC_MBIST_CNTRL 0xEC69D0
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#define mmTPC3_CFG_FUNC_MBIST_PAT 0xEC69D4
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_0 0xEC69D8
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_1 0xEC69DC
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_2 0xEC69E0
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_3 0xEC69E4
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#define mmTPC3_CFG_FUNC_MBIST_MEM_4 0xEC69E8
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_5 0xEC69EC
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_6 0xEC69F0
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#define mmTPC3_CFG_FUNC_MBIST_MEM_7 0xEC69F4
|
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#define mmTPC3_CFG_FUNC_MBIST_MEM_8 0xEC69F8
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|
#define mmTPC3_CFG_FUNC_MBIST_MEM_9 0xEC69FC
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#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_LOW 0xEC6A00
|
|
#define mmTPC3_CFG_QM_TENSOR_0_BASE_ADDR_HIGH 0xEC6A04
|
|
#define mmTPC3_CFG_QM_TENSOR_0_PADDING_VALUE 0xEC6A08
|
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#define mmTPC3_CFG_QM_TENSOR_0_TENSOR_CONFIG 0xEC6A0C
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_SIZE 0xEC6A10
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|
#define mmTPC3_CFG_QM_TENSOR_0_DIM_0_STRIDE 0xEC6A14
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_SIZE 0xEC6A18
|
|
#define mmTPC3_CFG_QM_TENSOR_0_DIM_1_STRIDE 0xEC6A1C
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_SIZE 0xEC6A20
|
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_2_STRIDE 0xEC6A24
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_SIZE 0xEC6A28
|
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_3_STRIDE 0xEC6A2C
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_SIZE 0xEC6A30
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#define mmTPC3_CFG_QM_TENSOR_0_DIM_4_STRIDE 0xEC6A34
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#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_LOW 0xEC6A38
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#define mmTPC3_CFG_QM_TENSOR_1_BASE_ADDR_HIGH 0xEC6A3C
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#define mmTPC3_CFG_QM_TENSOR_1_PADDING_VALUE 0xEC6A40
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#define mmTPC3_CFG_QM_TENSOR_1_TENSOR_CONFIG 0xEC6A44
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|
#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_SIZE 0xEC6A48
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_0_STRIDE 0xEC6A4C
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_SIZE 0xEC6A50
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_1_STRIDE 0xEC6A54
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_SIZE 0xEC6A58
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_2_STRIDE 0xEC6A5C
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_SIZE 0xEC6A60
|
|
#define mmTPC3_CFG_QM_TENSOR_1_DIM_3_STRIDE 0xEC6A64
|
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_SIZE 0xEC6A68
|
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#define mmTPC3_CFG_QM_TENSOR_1_DIM_4_STRIDE 0xEC6A6C
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#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_LOW 0xEC6A70
|
|
#define mmTPC3_CFG_QM_TENSOR_2_BASE_ADDR_HIGH 0xEC6A74
|
|
#define mmTPC3_CFG_QM_TENSOR_2_PADDING_VALUE 0xEC6A78
|
|
#define mmTPC3_CFG_QM_TENSOR_2_TENSOR_CONFIG 0xEC6A7C
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_SIZE 0xEC6A80
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_0_STRIDE 0xEC6A84
|
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#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_SIZE 0xEC6A88
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_1_STRIDE 0xEC6A8C
|
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#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_SIZE 0xEC6A90
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_2_STRIDE 0xEC6A94
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_SIZE 0xEC6A98
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_3_STRIDE 0xEC6A9C
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_SIZE 0xEC6AA0
|
|
#define mmTPC3_CFG_QM_TENSOR_2_DIM_4_STRIDE 0xEC6AA4
|
|
#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_LOW 0xEC6AA8
|
|
#define mmTPC3_CFG_QM_TENSOR_3_BASE_ADDR_HIGH 0xEC6AAC
|
|
#define mmTPC3_CFG_QM_TENSOR_3_PADDING_VALUE 0xEC6AB0
|
|
#define mmTPC3_CFG_QM_TENSOR_3_TENSOR_CONFIG 0xEC6AB4
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_SIZE 0xEC6AB8
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_0_STRIDE 0xEC6ABC
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_SIZE 0xEC6AC0
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_1_STRIDE 0xEC6AC4
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_SIZE 0xEC6AC8
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_2_STRIDE 0xEC6ACC
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_SIZE 0xEC6AD0
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_3_STRIDE 0xEC6AD4
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_SIZE 0xEC6AD8
|
|
#define mmTPC3_CFG_QM_TENSOR_3_DIM_4_STRIDE 0xEC6ADC
|
|
#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_LOW 0xEC6AE0
|
|
#define mmTPC3_CFG_QM_TENSOR_4_BASE_ADDR_HIGH 0xEC6AE4
|
|
#define mmTPC3_CFG_QM_TENSOR_4_PADDING_VALUE 0xEC6AE8
|
|
#define mmTPC3_CFG_QM_TENSOR_4_TENSOR_CONFIG 0xEC6AEC
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_SIZE 0xEC6AF0
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_0_STRIDE 0xEC6AF4
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_SIZE 0xEC6AF8
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_1_STRIDE 0xEC6AFC
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_SIZE 0xEC6B00
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_2_STRIDE 0xEC6B04
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_SIZE 0xEC6B08
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_3_STRIDE 0xEC6B0C
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_SIZE 0xEC6B10
|
|
#define mmTPC3_CFG_QM_TENSOR_4_DIM_4_STRIDE 0xEC6B14
|
|
#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_LOW 0xEC6B18
|
|
#define mmTPC3_CFG_QM_TENSOR_5_BASE_ADDR_HIGH 0xEC6B1C
|
|
#define mmTPC3_CFG_QM_TENSOR_5_PADDING_VALUE 0xEC6B20
|
|
#define mmTPC3_CFG_QM_TENSOR_5_TENSOR_CONFIG 0xEC6B24
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_SIZE 0xEC6B28
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_0_STRIDE 0xEC6B2C
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_SIZE 0xEC6B30
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_1_STRIDE 0xEC6B34
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_SIZE 0xEC6B38
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_2_STRIDE 0xEC6B3C
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_SIZE 0xEC6B40
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_3_STRIDE 0xEC6B44
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_SIZE 0xEC6B48
|
|
#define mmTPC3_CFG_QM_TENSOR_5_DIM_4_STRIDE 0xEC6B4C
|
|
#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_LOW 0xEC6B50
|
|
#define mmTPC3_CFG_QM_TENSOR_6_BASE_ADDR_HIGH 0xEC6B54
|
|
#define mmTPC3_CFG_QM_TENSOR_6_PADDING_VALUE 0xEC6B58
|
|
#define mmTPC3_CFG_QM_TENSOR_6_TENSOR_CONFIG 0xEC6B5C
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_SIZE 0xEC6B60
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_0_STRIDE 0xEC6B64
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_SIZE 0xEC6B68
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_1_STRIDE 0xEC6B6C
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_SIZE 0xEC6B70
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_2_STRIDE 0xEC6B74
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_SIZE 0xEC6B78
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_3_STRIDE 0xEC6B7C
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_SIZE 0xEC6B80
|
|
#define mmTPC3_CFG_QM_TENSOR_6_DIM_4_STRIDE 0xEC6B84
|
|
#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_LOW 0xEC6B88
|
|
#define mmTPC3_CFG_QM_TENSOR_7_BASE_ADDR_HIGH 0xEC6B8C
|
|
#define mmTPC3_CFG_QM_TENSOR_7_PADDING_VALUE 0xEC6B90
|
|
#define mmTPC3_CFG_QM_TENSOR_7_TENSOR_CONFIG 0xEC6B94
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_SIZE 0xEC6B98
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_0_STRIDE 0xEC6B9C
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_SIZE 0xEC6BA0
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_1_STRIDE 0xEC6BA4
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_SIZE 0xEC6BA8
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_2_STRIDE 0xEC6BAC
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_SIZE 0xEC6BB0
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_3_STRIDE 0xEC6BB4
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_SIZE 0xEC6BB8
|
|
#define mmTPC3_CFG_QM_TENSOR_7_DIM_4_STRIDE 0xEC6BBC
|
|
#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_LOW 0xEC6BC0
|
|
#define mmTPC3_CFG_QM_TENSOR_8_BASE_ADDR_HIGH 0xEC6BC4
|
|
#define mmTPC3_CFG_QM_TENSOR_8_PADDING_VALUE 0xEC6BC8
|
|
#define mmTPC3_CFG_QM_TENSOR_8_TENSOR_CONFIG 0xEC6BCC
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_SIZE 0xEC6BD0
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_0_STRIDE 0xEC6BD4
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_SIZE 0xEC6BD8
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_1_STRIDE 0xEC6BDC
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_SIZE 0xEC6BE0
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_2_STRIDE 0xEC6BE4
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_SIZE 0xEC6BE8
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_3_STRIDE 0xEC6BEC
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_SIZE 0xEC6BF0
|
|
#define mmTPC3_CFG_QM_TENSOR_8_DIM_4_STRIDE 0xEC6BF4
|
|
#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_LOW 0xEC6BF8
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#define mmTPC3_CFG_QM_TENSOR_9_BASE_ADDR_HIGH 0xEC6BFC
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#define mmTPC3_CFG_QM_TENSOR_9_PADDING_VALUE 0xEC6C00
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#define mmTPC3_CFG_QM_TENSOR_9_TENSOR_CONFIG 0xEC6C04
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_SIZE 0xEC6C08
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_0_STRIDE 0xEC6C0C
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_SIZE 0xEC6C10
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_1_STRIDE 0xEC6C14
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_SIZE 0xEC6C18
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_2_STRIDE 0xEC6C1C
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_SIZE 0xEC6C20
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_3_STRIDE 0xEC6C24
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_SIZE 0xEC6C28
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#define mmTPC3_CFG_QM_TENSOR_9_DIM_4_STRIDE 0xEC6C2C
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#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_LOW 0xEC6C30
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#define mmTPC3_CFG_QM_TENSOR_10_BASE_ADDR_HIGH 0xEC6C34
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#define mmTPC3_CFG_QM_TENSOR_10_PADDING_VALUE 0xEC6C38
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#define mmTPC3_CFG_QM_TENSOR_10_TENSOR_CONFIG 0xEC6C3C
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_SIZE 0xEC6C40
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_0_STRIDE 0xEC6C44
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_SIZE 0xEC6C48
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_1_STRIDE 0xEC6C4C
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_SIZE 0xEC6C50
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_2_STRIDE 0xEC6C54
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_SIZE 0xEC6C58
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_3_STRIDE 0xEC6C5C
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_SIZE 0xEC6C60
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#define mmTPC3_CFG_QM_TENSOR_10_DIM_4_STRIDE 0xEC6C64
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#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_LOW 0xEC6C68
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#define mmTPC3_CFG_QM_TENSOR_11_BASE_ADDR_HIGH 0xEC6C6C
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#define mmTPC3_CFG_QM_TENSOR_11_PADDING_VALUE 0xEC6C70
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#define mmTPC3_CFG_QM_TENSOR_11_TENSOR_CONFIG 0xEC6C74
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_SIZE 0xEC6C78
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_0_STRIDE 0xEC6C7C
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_SIZE 0xEC6C80
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_1_STRIDE 0xEC6C84
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_SIZE 0xEC6C88
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_2_STRIDE 0xEC6C8C
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_SIZE 0xEC6C90
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_3_STRIDE 0xEC6C94
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_SIZE 0xEC6C98
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#define mmTPC3_CFG_QM_TENSOR_11_DIM_4_STRIDE 0xEC6C9C
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#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_LOW 0xEC6CA0
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#define mmTPC3_CFG_QM_TENSOR_12_BASE_ADDR_HIGH 0xEC6CA4
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#define mmTPC3_CFG_QM_TENSOR_12_PADDING_VALUE 0xEC6CA8
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#define mmTPC3_CFG_QM_TENSOR_12_TENSOR_CONFIG 0xEC6CAC
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_SIZE 0xEC6CB0
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_0_STRIDE 0xEC6CB4
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_SIZE 0xEC6CB8
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_1_STRIDE 0xEC6CBC
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_SIZE 0xEC6CC0
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_2_STRIDE 0xEC6CC4
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_SIZE 0xEC6CC8
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_3_STRIDE 0xEC6CCC
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_SIZE 0xEC6CD0
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#define mmTPC3_CFG_QM_TENSOR_12_DIM_4_STRIDE 0xEC6CD4
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#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_LOW 0xEC6CD8
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#define mmTPC3_CFG_QM_TENSOR_13_BASE_ADDR_HIGH 0xEC6CDC
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#define mmTPC3_CFG_QM_TENSOR_13_PADDING_VALUE 0xEC6CE0
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#define mmTPC3_CFG_QM_TENSOR_13_TENSOR_CONFIG 0xEC6CE4
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_SIZE 0xEC6CE8
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_0_STRIDE 0xEC6CEC
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_SIZE 0xEC6CF0
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_1_STRIDE 0xEC6CF4
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_SIZE 0xEC6CF8
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_2_STRIDE 0xEC6CFC
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_SIZE 0xEC6D00
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_3_STRIDE 0xEC6D04
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_SIZE 0xEC6D08
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#define mmTPC3_CFG_QM_TENSOR_13_DIM_4_STRIDE 0xEC6D0C
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#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_LOW 0xEC6D10
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#define mmTPC3_CFG_QM_TENSOR_14_BASE_ADDR_HIGH 0xEC6D14
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#define mmTPC3_CFG_QM_TENSOR_14_PADDING_VALUE 0xEC6D18
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#define mmTPC3_CFG_QM_TENSOR_14_TENSOR_CONFIG 0xEC6D1C
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_SIZE 0xEC6D20
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_0_STRIDE 0xEC6D24
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_SIZE 0xEC6D28
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_1_STRIDE 0xEC6D2C
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_SIZE 0xEC6D30
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_2_STRIDE 0xEC6D34
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_SIZE 0xEC6D38
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_3_STRIDE 0xEC6D3C
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_SIZE 0xEC6D40
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#define mmTPC3_CFG_QM_TENSOR_14_DIM_4_STRIDE 0xEC6D44
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#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_LOW 0xEC6D48
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#define mmTPC3_CFG_QM_TENSOR_15_BASE_ADDR_HIGH 0xEC6D4C
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#define mmTPC3_CFG_QM_TENSOR_15_PADDING_VALUE 0xEC6D50
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#define mmTPC3_CFG_QM_TENSOR_15_TENSOR_CONFIG 0xEC6D54
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_SIZE 0xEC6D58
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_0_STRIDE 0xEC6D5C
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_SIZE 0xEC6D60
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_1_STRIDE 0xEC6D64
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_SIZE 0xEC6D68
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_2_STRIDE 0xEC6D6C
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_SIZE 0xEC6D70
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_3_STRIDE 0xEC6D74
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_SIZE 0xEC6D78
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#define mmTPC3_CFG_QM_TENSOR_15_DIM_4_STRIDE 0xEC6D7C
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#define mmTPC3_CFG_QM_SYNC_OBJECT_MESSAGE 0xEC6D80
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#define mmTPC3_CFG_QM_SYNC_OBJECT_ADDR 0xEC6D84
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#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_LOW 0xEC6D88
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#define mmTPC3_CFG_QM_KERNEL_BASE_ADDRESS_HIGH 0xEC6D8C
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#define mmTPC3_CFG_QM_TID_BASE_DIM_0 0xEC6D90
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#define mmTPC3_CFG_QM_TID_SIZE_DIM_0 0xEC6D94
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#define mmTPC3_CFG_QM_TID_BASE_DIM_1 0xEC6D98
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#define mmTPC3_CFG_QM_TID_SIZE_DIM_1 0xEC6D9C
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#define mmTPC3_CFG_QM_TID_BASE_DIM_2 0xEC6DA0
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#define mmTPC3_CFG_QM_TID_SIZE_DIM_2 0xEC6DA4
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#define mmTPC3_CFG_QM_TID_BASE_DIM_3 0xEC6DA8
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#define mmTPC3_CFG_QM_TID_SIZE_DIM_3 0xEC6DAC
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#define mmTPC3_CFG_QM_TID_BASE_DIM_4 0xEC6DB0
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#define mmTPC3_CFG_QM_TID_SIZE_DIM_4 0xEC6DB4
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#define mmTPC3_CFG_QM_KERNEL_CONFIG 0xEC6DB8
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#define mmTPC3_CFG_QM_KERNEL_ID 0xEC6DBC
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#define mmTPC3_CFG_QM_SRF_0 0xEC6DC0
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#define mmTPC3_CFG_QM_SRF_1 0xEC6DC4
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#define mmTPC3_CFG_QM_SRF_2 0xEC6DC8
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#define mmTPC3_CFG_QM_SRF_3 0xEC6DCC
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#define mmTPC3_CFG_QM_SRF_4 0xEC6DD0
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#define mmTPC3_CFG_QM_SRF_5 0xEC6DD4
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#define mmTPC3_CFG_QM_SRF_6 0xEC6DD8
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#define mmTPC3_CFG_QM_SRF_7 0xEC6DDC
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#define mmTPC3_CFG_QM_SRF_8 0xEC6DE0
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#define mmTPC3_CFG_QM_SRF_9 0xEC6DE4
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#define mmTPC3_CFG_QM_SRF_10 0xEC6DE8
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#define mmTPC3_CFG_QM_SRF_11 0xEC6DEC
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#define mmTPC3_CFG_QM_SRF_12 0xEC6DF0
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#define mmTPC3_CFG_QM_SRF_13 0xEC6DF4
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#define mmTPC3_CFG_QM_SRF_14 0xEC6DF8
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#define mmTPC3_CFG_QM_SRF_15 0xEC6DFC
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#define mmTPC3_CFG_QM_SRF_16 0xEC6E00
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#define mmTPC3_CFG_QM_SRF_17 0xEC6E04
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#define mmTPC3_CFG_QM_SRF_18 0xEC6E08
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#define mmTPC3_CFG_QM_SRF_19 0xEC6E0C
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#define mmTPC3_CFG_QM_SRF_20 0xEC6E10
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#define mmTPC3_CFG_QM_SRF_21 0xEC6E14
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#define mmTPC3_CFG_QM_SRF_22 0xEC6E18
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#define mmTPC3_CFG_QM_SRF_23 0xEC6E1C
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#define mmTPC3_CFG_QM_SRF_24 0xEC6E20
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#define mmTPC3_CFG_QM_SRF_25 0xEC6E24
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#define mmTPC3_CFG_QM_SRF_26 0xEC6E28
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#define mmTPC3_CFG_QM_SRF_27 0xEC6E2C
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#define mmTPC3_CFG_QM_SRF_28 0xEC6E30
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#define mmTPC3_CFG_QM_SRF_29 0xEC6E34
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#define mmTPC3_CFG_QM_SRF_30 0xEC6E38
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#define mmTPC3_CFG_QM_SRF_31 0xEC6E3C
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#endif /* ASIC_REG_TPC3_CFG_REGS_H_ */
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