/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Aptina Sensor PLL Configuration
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*
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* Copyright (C) 2012 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __APTINA_PLL_H
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#define __APTINA_PLL_H
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struct aptina_pll {
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unsigned int ext_clock;
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unsigned int pix_clock;
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unsigned int n;
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unsigned int m;
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unsigned int p1;
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};
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struct aptina_pll_limits {
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unsigned int ext_clock_min;
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unsigned int ext_clock_max;
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unsigned int int_clock_min;
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unsigned int int_clock_max;
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unsigned int out_clock_min;
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unsigned int out_clock_max;
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unsigned int pix_clock_max;
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unsigned int n_min;
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unsigned int n_max;
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unsigned int m_min;
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unsigned int m_max;
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unsigned int p1_min;
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unsigned int p1_max;
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};
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struct device;
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int aptina_pll_calculate(struct device *dev,
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const struct aptina_pll_limits *limits,
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struct aptina_pll *pll);
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#endif /* __APTINA_PLL_H */
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