/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "ior.h"
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#include <subdev/timer.h>
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static void
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tu102_sor_dp_vcpi(struct nvkm_ior *sor, int head,
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u8 slot, u8 slot_nr, u16 pbn, u16 aligned)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 hoff = head * 0x800;
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nvkm_mask(device, 0x61657c + hoff, 0xffffffff, (aligned << 16) | pbn);
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nvkm_mask(device, 0x616578 + hoff, 0x00003f3f, (slot_nr << 8) | slot);
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}
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static int
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tu102_sor_dp_links(struct nvkm_ior *sor, struct nvkm_i2c_aux *aux)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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const u32 loff = nv50_sor_link(sor);
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u32 dpctrl = 0x00000000;
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u32 clksor = 0x00000000;
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clksor |= sor->dp.bw << 18;
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dpctrl |= ((1 << sor->dp.nr) - 1) << 16;
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if (sor->dp.mst)
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dpctrl |= 0x40000000;
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if (sor->dp.ef)
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dpctrl |= 0x00004000;
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nvkm_mask(device, 0x612300 + soff, 0x007c0000, clksor);
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/*XXX*/
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nvkm_msec(device, 40, NVKM_DELAY);
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nvkm_mask(device, 0x612300 + soff, 0x00030000, 0x00010000);
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nvkm_mask(device, 0x61c10c + loff, 0x00000003, 0x00000001);
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nvkm_mask(device, 0x61c10c + loff, 0x401f4000, dpctrl);
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return 0;
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}
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static const struct nvkm_ior_func
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tu102_sor_hda = {
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.route = {
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.get = gm200_sor_route_get,
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.set = gm200_sor_route_set,
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},
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.state = gv100_sor_state,
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.power = nv50_sor_power,
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.clock = gf119_sor_clock,
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.hdmi = {
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.ctrl = gv100_hdmi_ctrl,
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.scdc = gm200_hdmi_scdc,
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},
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.dp = {
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.lanes = { 0, 1, 2, 3 },
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.links = tu102_sor_dp_links,
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.power = g94_sor_dp_power,
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.pattern = gm107_sor_dp_pattern,
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.drive = gm200_sor_dp_drive,
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.vcpi = tu102_sor_dp_vcpi,
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.audio = gv100_sor_dp_audio,
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.audio_sym = gv100_sor_dp_audio_sym,
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.watermark = gv100_sor_dp_watermark,
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},
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.hda = {
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.hpd = gf119_hda_hpd,
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.eld = gf119_hda_eld,
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.device_entry = gv100_hda_device_entry,
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},
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};
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static const struct nvkm_ior_func
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tu102_sor = {
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.route = {
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.get = gm200_sor_route_get,
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.set = gm200_sor_route_set,
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},
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.state = gv100_sor_state,
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.power = nv50_sor_power,
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.clock = gf119_sor_clock,
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.hdmi = {
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.ctrl = gv100_hdmi_ctrl,
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.scdc = gm200_hdmi_scdc,
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},
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.dp = {
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.lanes = { 0, 1, 2, 3 },
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.links = tu102_sor_dp_links,
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.power = g94_sor_dp_power,
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.pattern = gm107_sor_dp_pattern,
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.drive = gm200_sor_dp_drive,
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.vcpi = tu102_sor_dp_vcpi,
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.audio = gv100_sor_dp_audio,
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.audio_sym = gv100_sor_dp_audio_sym,
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.watermark = gv100_sor_dp_watermark,
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},
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};
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int
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tu102_sor_new(struct nvkm_disp *disp, int id)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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u32 hda = nvkm_rd32(device, 0x08a15c);
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if (hda & BIT(id))
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return nvkm_ior_new_(&tu102_sor_hda, disp, SOR, id);
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return nvkm_ior_new_(&tu102_sor, disp, SOR, id);
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}
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