/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*/
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#ifndef __DW_DSI_REG_H__
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#define __DW_DSI_REG_H__
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#define MASK(x) (BIT(x) - 1)
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#define DEFAULT_MAX_TX_ESC_CLK (10 * 1000000UL) //for hikey960
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/*
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* regs
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*/
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#define PWR_UP 0x04 /* Core power-up */
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#define RESET 0
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#define POWERUP BIT(0)
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#define PHY_IF_CFG 0xA4 /* D-PHY interface configuration */
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#define CLKMGR_CFG 0x08 /* the internal clock dividers */
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#define PHY_RSTZ 0xA0 /* D-PHY reset control */
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#define PHY_ENABLECLK BIT(2)
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#define PHY_UNRSTZ BIT(1)
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#define PHY_UNSHUTDOWNZ BIT(0)
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#define PHY_TST_CTRL0 0xB4 /* D-PHY test interface control 0 */
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#define PHY_TST_CTRL1 0xB8 /* D-PHY test interface control 1 */
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#define CLK_TLPX 0x10
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#define CLK_THS_PREPARE 0x11
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#define CLK_THS_ZERO 0x12
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#define CLK_THS_TRAIL 0x13
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#define CLK_TWAKEUP 0x14
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#define DATA_TLPX(x) (0x20 + ((x) << 4))
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#define DATA_THS_PREPARE(x) (0x21 + ((x) << 4))
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#define DATA_THS_ZERO(x) (0x22 + ((x) << 4))
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#define DATA_THS_TRAIL(x) (0x23 + ((x) << 4))
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#define DATA_TTA_GO(x) (0x24 + ((x) << 4))
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#define DATA_TTA_GET(x) (0x25 + ((x) << 4))
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#define DATA_TWAKEUP(x) (0x26 + ((x) << 4))
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#define PHY_CFG_I 0x60
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#define PHY_CFG_PLL_I 0x63
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#define PHY_CFG_PLL_II 0x64
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#define PHY_CFG_PLL_III 0x65
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#define PHY_CFG_PLL_IV 0x66
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#define PHY_CFG_PLL_V 0x67
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#define DPI_COLOR_CODING 0x10 /* DPI color coding */
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#define DPI_CFG_POL 0x14 /* DPI polarity configuration */
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#define VID_HSA_TIME 0x48 /* Horizontal Sync Active time */
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#define VID_HBP_TIME 0x4C /* Horizontal Back Porch time */
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#define VID_HLINE_TIME 0x50 /* Line time */
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#define VID_VSA_LINES 0x54 /* Vertical Sync Active period */
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#define VID_VBP_LINES 0x58 /* Vertical Back Porch period */
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#define VID_VFP_LINES 0x5C /* Vertical Front Porch period */
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#define VID_VACTIVE_LINES 0x60 /* Vertical resolution */
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#define VID_PKT_SIZE 0x3C /* Video packet size */
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#define VID_MODE_CFG 0x38 /* Video mode configuration */
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/***************************for hikey960***********************************/
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#define GEN_HDR 0x6c
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#define GEN_HDATA(data) (((data) & 0xffff) << 8)
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#define GEN_HDATA_MASK (0xffff << 8)
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#define GEN_HTYPE(type) (((type) & 0xff) << 0)
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#define GEN_HTYPE_MASK 0xff
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#define GEN_PLD_DATA 0x70
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#define CMD_PKT_STATUS 0x74
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#define GEN_CMD_EMPTY BIT(0)
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#define GEN_CMD_FULL BIT(1)
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#define GEN_PLD_W_EMPTY BIT(2)
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#define GEN_PLD_W_FULL BIT(3)
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#define GEN_PLD_R_EMPTY BIT(4)
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#define GEN_PLD_R_FULL BIT(5)
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#define GEN_RD_CMD_BUSY BIT(6)
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#define CMD_MODE_CFG 0x68
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#define MAX_RD_PKT_SIZE_LP BIT(24)
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#define DCS_LW_TX_LP BIT(19)
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#define DCS_SR_0P_TX_LP BIT(18)
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#define DCS_SW_1P_TX_LP BIT(17)
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#define DCS_SW_0P_TX_LP BIT(16)
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#define GEN_LW_TX_LP BIT(14)
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#define GEN_SR_2P_TX_LP BIT(13)
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#define GEN_SR_1P_TX_LP BIT(12)
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#define GEN_SR_0P_TX_LP BIT(11)
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#define GEN_SW_2P_TX_LP BIT(10)
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#define GEN_SW_1P_TX_LP BIT(9)
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#define GEN_SW_0P_TX_LP BIT(8)
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#define EN_ACK_RQST BIT(1)
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#define EN_TEAR_FX BIT(0)
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#define CMD_PKT_STATUS_TIMEOUT_US 20000
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#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
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DCS_LW_TX_LP | \
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DCS_SR_0P_TX_LP | \
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DCS_SW_1P_TX_LP | \
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DCS_SW_0P_TX_LP | \
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GEN_LW_TX_LP | \
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GEN_SR_2P_TX_LP | \
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GEN_SR_1P_TX_LP | \
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GEN_SR_0P_TX_LP | \
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GEN_SW_2P_TX_LP | \
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GEN_SW_1P_TX_LP | \
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GEN_SW_0P_TX_LP)
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/***************************for hikey960***********************************/
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#define PHY_TMR_CFG 0x9C /* Data lanes timing configuration */
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#define BTA_TO_CNT 0x8C /* Response timeout definition */
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#define PHY_TMR_LPCLK_CFG 0x98 /* clock lane timing configuration */
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#define CLK_DATA_TMR_CFG 0xCC
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#define LPCLK_CTRL 0x94 /* Low-power in clock lane */
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#define PHY_TXREQUESTCLKHS BIT(0)
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#define MODE_CFG 0x34 /* Video or Command mode selection */
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#define PHY_STATUS 0xB0 /* D-PHY PPI status interface */
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#define PHY_STOP_WAIT_TIME 0x30
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/*
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* regs relevant enum
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*/
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enum dpi_color_coding {
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DSI_24BITS_1 = 5,
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};
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enum dsi_video_mode_type {
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DSI_NON_BURST_SYNC_PULSES = 0,
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DSI_NON_BURST_SYNC_EVENTS,
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DSI_BURST_SYNC_PULSES_1,
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DSI_BURST_SYNC_PULSES_2
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};
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enum dsi_work_mode {
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DSI_VIDEO_MODE = 0,
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DSI_COMMAND_MODE
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};
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/*
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* Register Write/Read Helper functions
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*/
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static inline void dw_update_bits(void __iomem *addr, u32 bit_start,
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u32 mask, u32 val)
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{
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u32 tmp, orig;
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orig = readl(addr);
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tmp = orig & ~(mask << bit_start);
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tmp |= (val & mask) << bit_start;
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writel(tmp, addr);
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}
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#endif /* __DW_DRM_DSI_H__ */
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