/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __MACH_SDK7786_FPGA_H
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#define __MACH_SDK7786_FPGA_H
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#include <linux/io.h>
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#include <linux/types.h>
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#include <linux/bitops.h>
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#define SRSTR 0x000
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#define SRSTR_MAGIC 0x1971 /* Fixed magical read value */
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#define INTASR 0x010
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#define INTAMR 0x020
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#define MODSWR 0x030
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#define INTTESTR 0x040
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#define SYSSR 0x050
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#define NRGPR 0x060
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#define NMISR 0x070
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#define NMISR_MAN_NMI BIT(0)
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#define NMISR_AUX_NMI BIT(1)
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#define NMISR_MASK (NMISR_MAN_NMI | NMISR_AUX_NMI)
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#define NMIMR 0x080
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#define NMIMR_MAN_NMIM BIT(0) /* Manual NMI mask */
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#define NMIMR_AUX_NMIM BIT(1) /* Auxiliary NMI mask */
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#define NMIMR_MASK (NMIMR_MAN_NMIM | NMIMR_AUX_NMIM)
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#define INTBSR 0x090
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#define INTBMR 0x0a0
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#define USRLEDR 0x0b0
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#define MAPSWR 0x0c0
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#define FPGAVR 0x0d0
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#define FPGADR 0x0e0
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#define PCBRR 0x0f0
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#define RSR 0x100
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#define EXTASR 0x110
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#define SPCAR 0x120
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#define INTMSR 0x130
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#define PCIECR 0x140
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#define PCIECR_PCIEMUX1 BIT(15)
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#define PCIECR_PCIEMUX0 BIT(14)
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#define PCIECR_PRST4 BIT(12) /* slot 4 card present */
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#define PCIECR_PRST3 BIT(11) /* slot 3 card present */
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#define PCIECR_PRST2 BIT(10) /* slot 2 card present */
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#define PCIECR_PRST1 BIT(9) /* slot 1 card present */
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#define PCIECR_CLKEN BIT(4) /* oscillator enable */
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#define FAER 0x150
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#define USRGPIR 0x160
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/* 0x170 reserved */
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#define LCLASR 0x180
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#define LCLASR_FRAMEN BIT(15)
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#define LCLASR_FPGA_SEL_SHIFT 12
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#define LCLASR_NAND_SEL_SHIFT 8
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#define LCLASR_NORB_SEL_SHIFT 4
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#define LCLASR_NORA_SEL_SHIFT 0
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#define LCLASR_AREA_MASK 0x7
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#define LCLASR_FPGA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_FPGA_SEL_SHIFT)
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#define LCLASR_NAND_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NAND_SEL_SHIFT)
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#define LCLASR_NORB_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORB_SEL_SHIFT)
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#define LCLASR_NORA_SEL_MASK (LCLASR_AREA_MASK << LCLASR_NORA_SEL_SHIFT)
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#define SBCR 0x190
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#define SCBR_I2CMEN BIT(0) /* FPGA I2C master enable */
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#define SCBR_I2CCEN BIT(1) /* CPU I2C master enable */
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#define PWRCR 0x1a0
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#define PWRCR_SCISEL0 BIT(0)
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#define PWRCR_SCISEL1 BIT(1)
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#define PWRCR_SCIEN BIT(2) /* Serial port enable */
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#define PWRCR_PDWNACK BIT(5) /* Power down acknowledge */
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#define PWRCR_PDWNREQ BIT(7) /* Power down request */
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#define PWRCR_INT2 BIT(11) /* INT2 connection to power manager */
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#define PWRCR_BUPINIT BIT(13) /* DDR backup initialize */
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#define PWRCR_BKPRST BIT(15) /* Backup power reset */
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#define SPCBR 0x1b0
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#define SPICR 0x1c0
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#define SPIDR 0x1d0
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#define I2CCR 0x1e0
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#define I2CDR 0x1f0
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#define FPGACR 0x200
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#define IASELR1 0x210
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#define IASELR2 0x220
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#define IASELR3 0x230
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#define IASELR4 0x240
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#define IASELR5 0x250
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#define IASELR6 0x260
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#define IASELR7 0x270
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#define IASELR8 0x280
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#define IASELR9 0x290
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#define IASELR10 0x2a0
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#define IASELR11 0x2b0
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#define IASELR12 0x2c0
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#define IASELR13 0x2d0
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#define IASELR14 0x2e0
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#define IASELR15 0x2f0
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/* 0x300 reserved */
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#define IBSELR1 0x310
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#define IBSELR2 0x320
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#define IBSELR3 0x330
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#define IBSELR4 0x340
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#define IBSELR5 0x350
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#define IBSELR6 0x360
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#define IBSELR7 0x370
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#define IBSELR8 0x380
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#define IBSELR9 0x390
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#define IBSELR10 0x3a0
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#define IBSELR11 0x3b0
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#define IBSELR12 0x3c0
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#define IBSELR13 0x3d0
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#define IBSELR14 0x3e0
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#define IBSELR15 0x3f0
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#define USRACR 0x400
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#define BEEPR 0x410
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#define USRLCDR 0x420
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#define SMBCR 0x430
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#define SMBDR 0x440
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#define USBCR 0x450
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#define AMSR 0x460
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#define ACCR 0x470
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#define SDIFCR 0x480
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/* arch/sh/boards/mach-sdk7786/fpga.c */
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extern void __iomem *sdk7786_fpga_base;
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extern void sdk7786_fpga_init(void);
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/* arch/sh/boards/mach-sdk7786/nmi.c */
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extern void sdk7786_nmi_init(void);
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#define SDK7786_FPGA_REGADDR(reg) (sdk7786_fpga_base + (reg))
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/*
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* A convenience wrapper from register offset to internal I2C address,
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* when the FPGA is in I2C slave mode.
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*/
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#define SDK7786_FPGA_I2CADDR(reg) ((reg) >> 3)
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static inline u16 fpga_read_reg(unsigned int reg)
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{
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return ioread16(sdk7786_fpga_base + reg);
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}
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static inline void fpga_write_reg(u16 val, unsigned int reg)
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{
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iowrite16(val, sdk7786_fpga_base + reg);
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}
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#endif /* __MACH_SDK7786_FPGA_H */
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