Xilinx Video Test Pattern Generator (TPG)
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-----------------------------------------
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Required properties:
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- compatible: Must contain at least one of
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"xlnx,v-tpg-5.0" (TPG version 5.0)
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"xlnx,v-tpg-6.0" (TPG version 6.0)
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TPG versions backward-compatible with previous versions should list all
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compatible versions in the newer to older order.
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- reg: Physical base address and length of the registers set for the device.
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- clocks: Reference to the video core clock.
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- xlnx,video-format, xlnx,video-width: Video format and width, as defined in
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video.txt.
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- port: Video port, using the DT bindings defined in ../video-interfaces.txt.
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The TPG has a single output port numbered 0.
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Optional properties:
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- xlnx,vtc: A phandle referencing the Video Timing Controller that generates
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video timings for the TPG test patterns.
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- timing-gpios: Specifier for a GPIO that controls the timing mux at the TPG
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input. The GPIO active level corresponds to the selection of VTC-generated
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video timings.
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The xlnx,vtc and timing-gpios properties are mandatory when the TPG is
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synthesized with two ports and forbidden when synthesized with one port.
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Example:
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tpg_0: tpg@40050000 {
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compatible = "xlnx,v-tpg-6.0", "xlnx,v-tpg-5.0";
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reg = <0x40050000 0x10000>;
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clocks = <&clkc 15>;
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xlnx,vtc = <&vtc_3>;
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timing-gpios = <&ps7_gpio_0 55 GPIO_ACTIVE_LOW>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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xlnx,video-format = <XVIP_VF_YUV_422>;
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xlnx,video-width = <8>;
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tpg_in: endpoint {
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remote-endpoint = <&adv7611_out>;
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};
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};
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port@1 {
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reg = <1>;
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xlnx,video-format = <XVIP_VF_YUV_422>;
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xlnx,video-width = <8>;
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tpg1_out: endpoint {
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remote-endpoint = <&switch_in0>;
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};
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};
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};
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};
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