// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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max96712_dphy3_osc0: max96712-dphy3-oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96712-dphy3-osc0";
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};
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};
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&csi2_dphy1_hw {
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status = "okay";
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};
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&csi2_dphy3 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy3_in_max96712: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96712_dphy3_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy3_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi4_csi2_input>;
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};
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};
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};
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};
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&i2c6 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c6m3_xfer>;
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max96712_dphy3: max96712@29 {
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compatible = "maxim,max96712";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96712_dphy3_osc0 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dphy3_power>, <&max96712_dphy3_errb>, <&max96712_dphy3_lock>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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power-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>;
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pocen-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_HIGH>;
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lock-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
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auto-init-deskew-mask = <0x03>;
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frame-sync-period = <0>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "max96712";
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rockchip,camera-module-lens-name = "max96712";
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port {
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max96712_dphy3_out: endpoint {
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remote-endpoint = <&mipi_dphy3_in_max96712>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&mipi4_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi4_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy3_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi4_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi4_in>;
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};
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};
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};
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};
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&rkcif_mipi_lvds4 {
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status = "okay";
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/* parameters for do cif reset detecting:
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* index0: monitor mode,
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0 for idle,
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1 for continue,
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2 for trigger,
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3 for hotplug (for nextchip)
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* index1: the frame id to start timer,
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min is 2
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* index2: frame num of monitoring cycle
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* index3: err time for keep monitoring
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after finding out err (ms)
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* index4: csi2 err reference val for resetting
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*/
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rockchip,cif-monitor = <3 2 1 1000 5>;
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port {
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cif_mipi4_in: endpoint {
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remote-endpoint = <&mipi4_csi2_output>;
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};
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};
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};
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&rkcif {
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status = "okay";
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rockchip,android-usb-camerahal-enable;
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};
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&rkcif_mmu {
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status = "okay";
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};
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&pinctrl {
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max96712-dphy3 {
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max96712_dphy3_power: max96712-dphy3-power {
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rockchip,pins = <4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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max96712_dphy3_errb: max96712-dphy3-errb {
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rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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max96712_dphy3_lock: max96712-dphy3-lock {
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rockchip,pins = <3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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