// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/display/media-bus-format.h>
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/ {
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max96712_dcphy1_osc: max96712-dcphy1-oscillator {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96712-dcphy1-osc";
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};
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};
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&mipi_dcphy1 {
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status = "okay";
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};
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&csi2_dcphy1 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dcphy1_in_max96712: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96712_dcphy1_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidcphy1_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi1_csi2_input>;
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};
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};
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};
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};
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&i2c2 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2m4_xfer>;
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max96712_dcphy1: max96712@29 {
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compatible = "maxim4c,max96712";
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status = "okay";
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reg = <0x29>;
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clock-names = "xvclk";
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clocks = <&max96712_dcphy1_osc 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96712_dcphy1_pwdn>, <&max96712_dcphy1_errb>, <&max96712_dcphy1_lock>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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pwdn-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_HIGH>;
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pocen-gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
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lock-gpios = <&gpio4 RK_PD3 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "max96712";
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rockchip,camera-module-lens-name = "max96712";
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port {
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max96712_dcphy1_out: endpoint {
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remote-endpoint = <&mipi_dcphy1_in_max96712>;
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data-lanes = <1 2>;
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};
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};
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/* support mode config start */
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support-mode-config {
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status = "okay";
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bus-format = <MEDIA_BUS_FMT_UYVY8_2X8>;
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sensor-width = <1600>;
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sensor-height = <1300>;
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max-fps-numerator = <10000>;
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max-fps-denominator = <300000>;
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bpp = <16>;
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link-freq-idx = <20>;
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vc-array = <0x10 0x20 0x40 0x80>; // VC0~3: bit4~7
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};
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/* support mode config end */
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/* serdes local device start */
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serdes-local-device {
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status = "okay";
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/* GMSL LINK config start */
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gmsl-links {
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status = "okay";
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link-vdd-ldo1-en = <1>;
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link-vdd-ldo2-en = <1>;
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// Link A: link-id = 0
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gmsl-link-config-0 {
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status = "okay";
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link-id = <0>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <0>;
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link-tx-rate = <0>;
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port {
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max96712_dcphy1_link0_in: endpoint {
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remote-endpoint = <&max96712_dcphy1_remote0_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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14 D1 03 00 00 // VGAHiGain
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14 45 00 00 00 // Disable SSC
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];
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};
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};
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// Link B: link-id = 1
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gmsl-link-config-1 {
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status = "okay";
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link-id = <1>; // Link ID: 0/1/2/3
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link-type = <1>;
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link-rx-rate = <0>;
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link-tx-rate = <0>;
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port {
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max96712_dcphy1_link1_in: endpoint {
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remote-endpoint = <&max96712_dcphy1_remote1_out>;
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};
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};
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link-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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15 D1 03 00 00 // VGAHiGain
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15 45 00 00 00 // Disable SSC
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];
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};
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};
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};
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/* GMSL LINK config end */
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/* VIDEO PIPE config start */
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video-pipes {
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status = "okay";
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// Video Pipe 0
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video-pipe-config-0 {
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status = "okay";
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pipe-id = <0>; // Video Pipe ID: 0/1/2/3/4/5/6/7
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pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <0>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 0 to Controller 0
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09 0B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 2D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 0D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 0E 1e 00 00 // DST0 VC = 0, DT = YUV422 8bit
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09 0F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 10 00 00 00 // DST1 VC = 0, DT = Frame Start
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09 11 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 12 01 00 00 // DST2 VC = 0, DT = Frame End
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// pipe Cross
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01 D9 59 00 00 // pipe 0: Inverts Cross VS
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];
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};
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};
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// Video Pipe 1
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video-pipe-config-1 {
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status = "okay";
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pipe-id = <1>; // Video Pipe 1: pipe-id = 1
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pipe-idx = <0>; // Video Pipe X/Y/Z/U: 0/1/2/3
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link-idx = <1>; // Link A/B/C/D: 0/1/2/3
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pipe-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Send YUV422, FS, and FE from Video Pipe 1 to Controller 0
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09 4B 07 00 00 // Enable 0/1/2 SRC/DST Mappings
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09 6D 00 00 00 // SRC/DST 0/1/2 -> CSI2 Controller 0;
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// For the following MSB 2 bits = VC, LSB 6 bits = DT
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09 4D 1e 00 00 // SRC0 VC = 0, DT = YUV422 8bit
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09 4E 5e 00 00 // DST0 VC = 1, DT = YUV422 8bit
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09 4F 00 00 00 // SRC1 VC = 0, DT = Frame Start
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09 50 40 00 00 // DST1 VC = 1, DT = Frame Start
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09 51 01 00 00 // SRC2 VC = 0, DT = Frame End
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09 52 41 00 00 // DST2 VC = 1, DT = Frame End
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// pipe Cross
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01 F9 59 00 00 // pipe 1: Inverts Cross VS
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];
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};
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};
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// Software override for parallel mode
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parallel-mode-config {
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status = "okay";
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parallel-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// Enable software override for all pipes since GMSL1 data is parallel mode, bpp=8, dt=0x1e(yuv-8)
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04 1A f0 00 00 // pipe 0/1/2/3: Enable YUV8-/10-bit mux mode
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04 0B 40 00 00 // pipe 0 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
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04 0C 00 00 00 // pipe 0 and 1 VC software override: 0x00
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04 0D 00 00 00 // pipe 2 and 3 VC software override: 0x00
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04 0E 5e 00 00 // pipe 0 DT=0x1E: YUV422 8-bit
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04 0F 7e 00 00 // pipe 1 DT=0x1E: YUV422 8-bit
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04 10 7a 00 00 // pipe 2 DT=0x1E, pipe 3 DT=0x1E: YUV422 8-bit
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04 11 48 00 00 // pipe 1 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
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04 12 20 00 00 // pipe 2 bpp=0x08, pipe 3 bpp=0x08: Datatypes = 0x2A, 0x10-12, 0x31-37
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04 15 c0 c0 00 // pipe 0/1 enable software overide
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04 18 c0 c0 00 // pipe 2/3 enable software overide
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];
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};
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};
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};
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/* VIDEO PIPE config end */
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/* MIPI TXPHY config start */
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mipi-txphys {
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status = "okay";
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phy-mode = <1>;
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phy-force-clock-out = <1>;
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phy-force-clk0-en = <0>;
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phy-force-clk3-en = <0>;
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// MIPI TXPHY A: phy-id = 0
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mipi-txphy-config-0 {
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status = "okay";
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phy-id = <0>; // MIPI TXPHY ID: 0/1/2/3
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phy-type = <0>;
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auto-deskew = <0x00>;
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data-lane-num = <2>;
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data-lane-map = <0x4>;
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vc-ext-en = <0>;
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};
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};
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/* MIPI TXPHY config end */
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/* local device extra init sequence */
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extra-init-sequence {
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status = "disabled";
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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// common init sequence such as fsync / gpio and so on
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];
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};
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};
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/* serdes local device end */
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/* serdes remote device start */
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serdes-remote-device-0 {
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compatible = "maxim4c,link0,max9295";
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status = "okay";
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remote-id = <0>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x41>; // 0: disable remap
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port {
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max96712_dcphy1_remote0_out: endpoint {
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remote-endpoint = <&max96712_dcphy1_link0_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
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00 11 03 00 00 // Coax Drive
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02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
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03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
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00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
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00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
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02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
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02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
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00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
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00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
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00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
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01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
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01 01 50 00 00 // Video X, BPP = 0x10
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00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
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00 02 13 00 00 // Video transmit enable for Port X
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];
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};
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};
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serdes-remote-device-1 {
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compatible = "maxim4c,link1,max9295";
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status = "okay";
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remote-id = <1>; // Same as Link ID: 0/1/2/3
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// Serializer i2c 7bit address remap
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ser-i2c-addr-def = <0x40>;
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ser-i2c-addr-map = <0x42>; // 0: disable remap
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port {
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max96712_dcphy1_remote1_out: endpoint {
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remote-endpoint = <&max96712_dcphy1_link1_in>;
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};
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};
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remote-init-sequence {
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seq-item-size = <5>; // reg-addr-len + reg-val-len * 2 + 1
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reg-addr-len = <2>; // 1: 8bits, 2: 16bits
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reg-val-len = <1>; // 1: 8bits, 2: 16bits, 3: 24bits
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// reg_addr reg_val val_mask delay
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init-sequence = [
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00 01 04 00 00 // RX_RATE: 187.5Mbps, TX_RATE: 3Gbps
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00 11 03 00 00 // Coax Drive
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02 D6 03 00 00 // MFP8: GPIO_OUT_DIS = 1, GPIO_TX_EN = 1
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03 F0 51 00 00 // RCLK: 27MHz/24MHz (ALT),Enable reference-generation PLL, Enable pre-defined clock setting for reference-generation PLL
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00 03 07 00 00 // RCLK: Enable RCLK output from altermative MFP pin, RCLKOUT clock select reference PLL
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00 06 b1 00 00 // RCLK: GMSL2, Enable RCLK output, i2c selected
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02 C1 10 00 00 // MFP1: GPIO_OUT pin output is driven to 1 when GPIO_RX_EN = 0
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02 C2 60 00 00 // MFP1: OUT_TYPE = 1: Push-pull, PULL_UPDN_SEL[1:0] = 0b01: Pullup
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00 07 07 00 00 // Enable Parallel video input, Parallel HS and VS Enable
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00 10 05 00 00 // AUTO_LINK = 0, LINK_CFG = 1: LinkA is selected, REG_ENABLE = 1: Regulator enabled
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00 12 14 00 00 // REG_MNL = 1: Enable LDO on/off state controlled by REG_ENABLE
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01 00 62 00 00 // Video X, Line CRC enabled, ENC_MODE = 2: HS, VS, DE encoding on, color bits sent only when DE is high
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01 01 50 00 00 // Video X, BPP = 0x10
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00 53 10 00 00 // Video X, TX_STR_SEL = 0: Stream ID = 0 for packets from this channel
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00 02 13 00 00 // Video transmit enable for Port X
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];
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};
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};
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/* serdes remote device end */
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};
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};
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&mipi1_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidcphy1_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi1_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi1_in>;
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};
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};
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};
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};
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&rkcif_mipi_lvds1 {
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status = "okay";
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/* parameters for do cif reset detecting:
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* index0: monitor mode,
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0 for idle,
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1 for continue,
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2 for trigger,
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3 for hotplug (for nextchip)
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* index1: the frame id to start timer,
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min is 2
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* index2: frame num of monitoring cycle
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* index3: err time for keep monitoring
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after finding out err (ms)
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* index4: csi2 err reference val for resetting
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*/
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rockchip,cif-monitor = <3 2 1 1000 5>;
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port {
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cif_mipi1_in: endpoint {
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remote-endpoint = <&mipi1_csi2_output>;
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};
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};
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};
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&rkcif {
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status = "okay";
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rockchip,android-usb-camerahal-enable;
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};
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&rkcif_mmu {
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status = "okay";
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};
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&pinctrl {
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max96712-dcphy1 {
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max96712_dcphy1_pwdn: max96712-dcphy1-pwdn {
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rockchip,pins = <4 RK_PD1 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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max96712_dcphy1_errb: max96712-dcphy1-errb {
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rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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max96712_dcphy1_lock: max96712-dcphy1-lock {
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rockchip,pins = <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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};
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