/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _PHL_TRX_MIT_C_
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#include "phl_headers.h"
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#if defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN)
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enum rtw_phl_status phl_pcie_trx_mit_start(struct phl_info_t *phl_info,
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u8 dispr_idx)
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{
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struct rtw_pcie_trx_mit_info_t info = {0};
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if (dispr_idx != HW_BAND_0)
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return RTW_PHL_STATUS_SUCCESS;
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PHL_INFO("%s :: pcie trx interrupt mitigation off\n", __func__);
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if (RTW_HAL_STATUS_SUCCESS !=
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rtw_hal_pcie_trx_mit(phl_info->hal, info.tx_timer, info.tx_counter,
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info.rx_timer, info.rx_counter))
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return RTW_PHL_STATUS_FAILURE;
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return RTW_PHL_STATUS_SUCCESS;
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}
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enum rtw_phl_status
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phl_evt_pcie_trx_mit_hdlr(struct phl_info_t *phl_info, u8 *mit_info)
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{
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struct rtw_pcie_trx_mit_info_t *info = (struct rtw_pcie_trx_mit_info_t *)mit_info;
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PHL_INFO("%s :: tx_timer == %d us, tx_counter = %d, rx_timer == %d us, "
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"rx_counter = %d, fixed_mitigation=%d\n",
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__func__, info->tx_timer, info->tx_counter, info->rx_timer,
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info->rx_counter, info->fixed_mitigation);
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if (RTW_HAL_STATUS_SUCCESS !=
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rtw_hal_pcie_trx_mit(phl_info->hal, info->tx_timer,
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info->tx_counter, info->rx_timer,
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info->rx_counter))
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return RTW_PHL_STATUS_FAILURE;
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phl_info->hci->fixed_mitigation = info->fixed_mitigation;
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return RTW_PHL_STATUS_SUCCESS;
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}
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static void _phl_pcie_trx_mit_done(void *drv_priv, u8 *cmd, u32 cmd_len, enum rtw_phl_status status)
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{
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if (cmd) {
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_os_mem_free(drv_priv, cmd, cmd_len);
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cmd = NULL;
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}
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}
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static enum rtw_phl_status
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phl_pcie_trx_mit(struct phl_info_t *phl_info,
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u32 tx_timer, u8 tx_counter, u32 rx_timer, u8 rx_counter)
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{
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#ifdef CONFIG_CMD_DISP
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void *drv_priv = phl_to_drvpriv(phl_info);
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struct rtw_pcie_trx_mit_info_t *info = NULL;
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enum rtw_phl_status psts = RTW_PHL_STATUS_FAILURE;
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u32 info_len = sizeof(struct rtw_pcie_trx_mit_info_t);
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info = _os_mem_alloc(drv_priv, info_len);
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if (info == NULL) {
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PHL_ERR("%s: alloc mit_info failed!\n", __func__);
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goto _exit;
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}
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info->tx_timer = tx_timer;
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info->tx_counter = tx_counter;
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info->rx_timer = rx_timer;
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info->rx_counter = rx_counter;
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psts = phl_cmd_enqueue(phl_info,
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HW_BAND_0,
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MSG_EVT_PCIE_TRX_MIT,
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(u8 *)info,
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info_len,
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_phl_pcie_trx_mit_done,
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PHL_CMD_NO_WAIT,
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0);
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if (is_cmd_failure(psts)) {
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/* Send cmd success, but wait cmd fail*/
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psts = RTW_PHL_STATUS_FAILURE;
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} else if (psts != RTW_PHL_STATUS_SUCCESS) {
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/* Send cmd fail */
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psts = RTW_PHL_STATUS_FAILURE;
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_os_mem_free(drv_priv, info, info_len);
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}
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_exit:
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return psts;
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#else
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PHL_ERR("phl_fsm not support %s\n", __func__);
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return RTW_PHL_STATUS_FAILURE;
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#endif /*CONFIG_CMD_DISP*/
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}
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void phl_pcie_trx_mit_watchdog(struct phl_info_t *phl_info)
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{
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static enum rtw_tfc_lvl rx_traffic_lvl = RTW_TFC_IDLE;
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struct rtw_stats *phl_stats = &phl_info->phl_com->phl_stats;
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if (phl_info->hci->fixed_mitigation == 1)
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return;
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if (rx_traffic_lvl == phl_stats->rx_traffic.lvl)
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return;
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rx_traffic_lvl = phl_stats->rx_traffic.lvl;
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if (rx_traffic_lvl == RTW_TFC_HIGH)
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phl_pcie_trx_mit(phl_info, 0, 0,
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phl_info->hci->rx_mit_timer_high,
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phl_info->hci->rx_mit_counter_high);
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else
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phl_pcie_trx_mit(phl_info, 0, 0, 0, 0);
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}
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void rtw_phl_pcie_trx_mit_cfg(void *phl,
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struct rtw_pcie_trx_mit_info_t *mit_info)
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{
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struct phl_info_t *phl_info = (struct phl_info_t *)phl;
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PHL_INFO("%s :: rx_mit_counter_high == %d, rx_mit_timer_high == %d\n",
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__func__, mit_info->rx_mit_counter_high,
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mit_info->rx_mit_timer_high);
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phl_info->hci->fixed_mitigation = mit_info->fixed_mitigation;
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phl_info->hci->rx_mit_counter_high = mit_info->rx_mit_counter_high;
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phl_info->hci->rx_mit_timer_high = mit_info->rx_mit_timer_high;
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}
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#endif /*defined(CONFIG_PCI_HCI) && defined(PCIE_TRX_MIT_EN)*/
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