/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef __PHL_TRX_DEF_H_
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#define __PHL_TRX_DEF_H_
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/* core / phl common structrue */
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#ifndef MAX_PHL_TX_RING_ENTRY_NUM
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#define MAX_PHL_TX_RING_ENTRY_NUM 4096
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#endif /*MAX_PHL_TX_RING_ENTRY_NUM*/
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#ifndef MAX_PHL_RX_RING_ENTRY_NUM
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#define MAX_PHL_RX_RING_ENTRY_NUM 4096
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#endif /*MAX_PHL_RX_RING_ENTRY_NUM*/
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#define MAX_PHL_RING_CAT_NUM 10 /* 8 tid + 1 mgnt + 1 hiq*/
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#ifdef CONFIG_RTW_REDUCE_MEM
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#define MAX_PHL_RING_RX_PKT_NUM MAX_PHL_RX_RING_ENTRY_NUM
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#else
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#define MAX_PHL_RING_RX_PKT_NUM 8192
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#endif /*CONFIG_RTW_REDUCE_MEM*/
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#define MAX_RX_BUF_SEG_NUM 4
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#if defined(CONFIG_VW_REFINE) || defined(CONFIG_ONE_TXQ)
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#define _H2CB_CMD_QLEN 256
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#define _H2CB_DATA_QLEN 256
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#else
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#define _H2CB_CMD_QLEN 32
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#define _H2CB_DATA_QLEN 32
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#endif
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#define _H2CB_LONG_DATA_QLEN 200 /* should be refined */
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#define MAX_H2C_PKT_NUM (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN + _H2CB_LONG_DATA_QLEN)
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#define FWCMD_HDR_LEN 8
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#define _WD_BODY_LEN 24
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#define H2C_CMD_LEN 64
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#define H2C_DATA_LEN 256
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#define H2C_LONG_DATA_LEN 2048
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#define get_h2c_size_by_range(i) \
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((i < _H2CB_CMD_QLEN) ? \
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(FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_CMD_LEN) : \
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((i < (_H2CB_CMD_QLEN + _H2CB_DATA_QLEN)) ? \
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(FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_DATA_LEN) : \
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(FWCMD_HDR_LEN + _WD_BODY_LEN + H2C_LONG_DATA_LEN)))
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struct rtw_h2c_pkt {
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_os_list list;
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u8 *vir_head; /* should not reset */
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u8 *vir_data;
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u8 *vir_end;
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u8 *vir_tail;
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void *os_rsvd[1];
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u8 type;
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u32 id; /* h2c id */
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u32 buf_len;
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u32 data_len;
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u32 phy_addr_l;
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u32 phy_addr_h;
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u8 cache;
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u16 host_idx;
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u8 h2c_seq; /* h2c seq */
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};
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/**
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* the category of phl ring
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*/
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enum rtw_phl_ring_cat {
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RTW_PHL_RING_CAT_TID0 = 0,
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RTW_PHL_RING_CAT_TID1 = 1,
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RTW_PHL_RING_CAT_TID2 = 2,
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RTW_PHL_RING_CAT_TID3 = 3,
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RTW_PHL_RING_CAT_TID4 = 4,
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RTW_PHL_RING_CAT_TID5 = 5,
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RTW_PHL_RING_CAT_TID6 = 6,
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RTW_PHL_RING_CAT_TID7 = 7,
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RTW_PHL_RING_CAT_MGNT = 8,
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RTW_PHL_RING_CAT_HIQ = 9,
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RTW_PHL_RING_CAT_MAX = 0xff
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};
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/**
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* @RTW_PHL_TREQ_TYPE_NORMAL:
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* normal tx request
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* @RTW_PHL_TREQ_TYPE_TEST_PATTERN:
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* this tx request is a test pattern generated by test suite
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* @RTW_PHL_TREQ_TYPE_CORE_TXSC:
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* it means this txreq is a shortcut pkt, so it need a txsc recycle
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* @RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC:
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* it means this txreq is a new cache in core layer and also need cache
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* in phl layer
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* @RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC:
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* this is for phl tx shortcut entry to update
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*/
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enum rtw_treq_type {
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RTW_PHL_TREQ_TYPE_NORMAL = 0,
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RTW_PHL_TREQ_TYPE_TEST_PATTERN = 1,
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#if defined(CONFIG_CORE_TXSC) || defined(CONFIG_PHL_TXSC)
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RTW_PHL_TREQ_TYPE_CORE_TXSC = 2,
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RTW_PHL_TREQ_TYPE_PHL_ADD_TXSC = 3,
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RTW_PHL_TREQ_TYPE_PHL_UPDATE_TXSC = 0x80,
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#endif
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RTW_PHL_TREQ_TYPE_MAX = 0xFF
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};
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enum rtw_packet_type {
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RTW_PHL_PKT_TYPE_DATA = 0,
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RTW_PHL_PKT_TYPE_MGNT = 1,
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RTW_PHL_PKT_TYPE_H2C = 2,
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RTW_PHL_PKT_TYPE_CTRL = 3,
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RTW_PHL_PKT_TYPE_FWDL = 4,
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RTW_PHL_PKT_TYPE_MAX = 0xFF
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};
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/**
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* struct rtw_t_mdata_non_dcpu:
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* this settings are only used in non-dcpu mode.
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*/
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struct rtw_t_mdata_non_dcpu {
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u8 tbd;
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};
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/**
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* struct rtw_t_mdata_dcpu:
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* this settings are only used in dcpu mode.
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*/
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struct rtw_t_mdata_dcpu {
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u8 tbd;
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};
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/**
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* tx packet descrption
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*
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* @u: the union separates dpcu mode and non-dpcu mode unique settings
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* @mac_priv: the mac private struture only used by HV tool.
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* normal driver won't allocate memory for this pointer.
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*/
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struct rtw_t_meta_data {
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bool wdfmt_dbg;
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/* basic */
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u8 *ta;
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u8 *ra;
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u8 da[6];
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u8 sa[6];
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u8 to_ds;
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u8 from_ds;
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u8 band; /*0 or 1*/
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u8 wmm; /*0 or 1*/
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enum rtw_packet_type type;
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u8 tid;
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u16 pktlen; /* MAC header length + frame body length */
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enum rtw_phl_ring_cat cat;
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/* body section start */
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u16 macid;
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/* sequence */
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u8 hw_seq_mode;
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u8 hw_ssn_sel;
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u16 sw_seq;
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/*checksum offload*/
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u8 chk_en;
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/* hdr conversion & hw amsdu */
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u8 smh_en;
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u8 hw_amsdu;
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u8 hdr_len;
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u8 wp_offset;
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u8 shcut_camid;
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u8 upd_wlan_hdr;
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u8 reuse_start_num;
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u8 reuse_size;
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u8 a4_hdr;
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u8 hci_seqnum_mode;
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u8 msdu_num;
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/* dma */
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u8 dma_ch;
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u8 wd_page_size;
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u8 wdinfo_en;
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u8 addr_info_num;
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u8 usb_pkt_ofst;
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u8 usb_txagg_num;
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/* ampdu */
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u8 ampdu_en;
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u8 bk;
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/* sec */
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u8 hw_sec_iv;
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u8 sw_sec_iv;
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u8 sec_keyid;
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u8 iv[6];
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/* mlo */
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u8 sw_mld_en;
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/* misc */
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u8 no_ack;
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u8 eosp_bit;
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u8 more_data;
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/* body section end */
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/* body or info section start */
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/* rate */
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u8 data_bw_er;
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u8 f_dcm;
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u8 f_er;
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u16 f_rate;
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u8 f_gi_ltf;
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u8 f_bw;
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u8 userate_sel;
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/* a ctrl */
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u8 a_ctrl_uph;
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/* sec */
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u8 sec_hw_enc;
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u8 sec_type;
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u8 force_key_en;
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/* misc */
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u8 bc;
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u8 mc;
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/* body or info section end */
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/* info section start */
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/* rate */
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u8 f_ldpc;
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u8 f_stbc;
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/* tx cnt & rty rate */
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u8 dis_rts_rate_fb;
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u8 dis_data_rate_fb;
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u16 data_rty_lowest_rate;
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u8 data_tx_cnt_lmt;
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u8 data_tx_cnt_lmt_en;
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/* ampdu */
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u16 max_agg_num;
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u8 ampdu_density;
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/* a ctrl */
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u8 a_ctrl_bqr;
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u8 a_ctrl_bsr;
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u8 a_ctrl_cas;
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/* sec */
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u8 sec_cam_idx;
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/* protection */
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u8 rts_en;
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u8 cts2self;
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u8 rts_cca_mode;
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u8 hw_rts_en;
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/* misc */
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u8 mbssid;
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u8 hal_port;
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u8 nav_use_hdr;
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u8 ack_ch_info;
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u8 life_time_sel;
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u8 ndpa;
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u8 f_bypass_punc;
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u8 puncture_pattern_en;
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u16 puncture_pattern;
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u8 signaling_ta_pkt_en;
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u8 snd_pkt_sel;
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u8 sifs_tx;
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u8 rtt_en;
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u8 spe_rpt;
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u8 raw;
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u8 sw_define;
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u8 sw_tx_ok;
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/* info section end */
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union {
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struct rtw_t_mdata_non_dcpu non_dcpu;
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struct rtw_t_mdata_dcpu dcpu;
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} u;
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void *mac_priv;
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};
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/**
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* packet recv information
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*/
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struct rtw_r_meta_data {
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u8 dma_ch;
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u8 hal_port;
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u8 ta[6]; /* Transmitter Address */
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u8 ppdu_cnt_chg;
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#ifdef CONFIG_PHL_CSUM_OFFLOAD_RX
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u8 chksum_status; /*return mac_chk_rx_tcpip_chksum_ofd,0 is ok ,1 is fail*/
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#endif
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u8 rx_deferred_release;
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#ifdef CONFIG_PHL_TDLS
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u8 is_tdls_frame;
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#endif
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u16 pktlen;
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u8 shift;
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u8 wl_hd_iv_len;
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u8 bb_sel;
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u8 mac_info_vld;
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u8 rpkt_type;
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u8 drv_info_size;
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u8 long_rxd;
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u8 ppdu_type;
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u8 ppdu_cnt;
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u8 sr_en;
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u8 user_id;
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u16 rx_rate;
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u8 rx_gi_ltf;
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u8 non_srg_ppdu;
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u8 inter_ppdu;
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u8 bw;
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u32 freerun_cnt;
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u8 a1_match;
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u8 sw_dec;
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u8 hw_dec;
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u8 ampdu;
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u8 ampdu_end_pkt;
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u8 amsdu;
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u8 amsdu_cut;
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u8 last_msdu;
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u8 bypass;
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u8 crc32;
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u8 icverr;
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u8 magic_wake;
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u8 unicast_wake;
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u8 pattern_wake;
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u8 get_ch_info;
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u8 pattern_idx;
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u8 target_idc;
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u8 chksum_ofld_en;
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u8 with_llc;
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u8 rx_statistics;
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u8 bip_keyid;
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u8 bip_enc;
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u8 is_da;
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u8 reorder;
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u8 a4_frame;
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u8 frame_type;
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u8 mc;
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u8 bc;
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u8 more_data;
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u8 more_frag;
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u8 pwr_bit;
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u8 qos;
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u8 tid;
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u8 eosp;
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u8 htc;
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u8 q_null;
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u16 seq;
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u8 frag_num;
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u8 sec_cam_idx;
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u8 addr_cam;
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u16 macid;
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u8 rx_pl_id;
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u8 addr_cam_vld;
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u8 addr_fwd_en;
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u8 rx_pl_match;
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u8 mac_addr[6];
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u8 smart_ant;
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u8 sec_type;
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u8 hdr_cnv;
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u8 hdr_offset;
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u8 hdr_cnv_size;
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u8 rxsc_entry;
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u8 rxsc_hit;
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u8 nat25_hit;
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u8 phy_rpt_en;
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u8 phy_rpt_size;
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u16 pkt_id;
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u8 fwd_target;
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u8 bcn_fw_info;
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u8 fw_rls;
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};
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/**
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* rtw_pkt_buf_list -- store pakcet from upper layer(ex. ndis, kernel, ethernet..)
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* @vir_addr: virtual address of this packet
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* @phy_addr_l: lower 32-bit physical address of this packet
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* @phy_addr_h: higher 32-bit physical address of this packet
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* @length: length of this packet
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* @type: tbd
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*/
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struct rtw_pkt_buf_list {
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u8 *vir_addr;
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u32 phy_addr_l;
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u32 phy_addr_h;
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u16 length;
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};
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#ifdef CONFIG_PHL_TX_DBG
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typedef
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void
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(*CORE_TX_HANDLE_CALLBACK)
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(
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void *drv_priv,
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void *pctx,
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bool btx_ok
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);
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/**
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* @en_dbg: if en_dbg = true, phl tx will print tx dbg info for this dbg pkt. set the flag from core layer.
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* @tx_dbg_pkt_type: Identification type, define by core layer
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* @core_add_tx_t: core layer add tx req to phl time
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* @enq_pending_wd_t: phl tx enqueue pending wd page time
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* @recycle_wd_t: phl tx handle the wp report and recycle wd time
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*/
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struct rtw_tx_dbg {
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bool en_dbg;
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u16 tx_dbg_pkt_type;
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u32 core_add_tx_t;
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u32 enq_pending_wd_t;
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u32 recycle_wd_t;
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CORE_TX_HANDLE_CALLBACK statecb;
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void *pctx;
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};
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#endif /* CONFIG_PHL_TX_DBG */
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enum rtw_tx_status {
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TX_STATUS_TX_DONE,
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TX_STATUS_TX_FAIL_REACH_RTY_LMT,
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TX_STATUS_TX_FAIL_LIFETIME_DROP,
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TX_STATUS_TX_FAIL_MACID_DROP,
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TX_STATUS_TX_FAIL_SW_DROP,
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TX_STATUS_TX_FAIL_FORCE_DROP_BY_STUCK,
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TX_STATUS_TX_FAIL_MAX
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};
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/**
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* context for tx feedback handler
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* @drvpriv: driver private
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* @ctx: private context
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* @id: module id of this tx packet
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* @txsts: detail tx status
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* @txfb_cb: tx feedback handler, currently assign by core layer
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*/
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struct rtw_txfb_t {
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void *drvpriv;
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void *ctx;
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enum phl_module_id id;
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enum rtw_tx_status txsts;
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void (*txfb_cb)(struct rtw_txfb_t *txfb);
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};
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/**
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* the local buffer from core layer
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* @vir_addr: virtual address of this packet
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* @phy_addr_l: lower 32-bit physical address of this packet
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* @phy_addr_h: higher 32-bit physical address of this packet
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* @used_size: record used size of this local buffer
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* @buf_max_size: MAXIMUM size of this local buffer, shall be assigned by core
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* @os_priv: the private context from core layer
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* @pkt_cnt: count of pkt list from tx_req
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* @pkt_list: address of pkt list (keep this to be last one)
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*/
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struct tx_local_buf {
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u8 *vir_addr;
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u32 phy_addr_l;
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u32 phy_addr_h;
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u32 used_size;
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u32 buf_max_size;
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u8 cache;
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void *os_priv;
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#ifdef RTW_TX_COALESCE_BAK_PKT_LIST
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u8 pkt_cnt;
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struct rtw_pkt_buf_list pkt_list[0];
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#endif
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};
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/**
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* the xmit request from core layer, store in xmit phl ring
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* @list: list
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* @os_priv: the private context from core layer
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* @mdata: see structure rtw_t_meta_data
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* @tx_time: xmit requset tx time, unit in ms
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* @shortcut_id: short cut id this packet will use in phl/hal
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* @total_len: the total length of pkt_list
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* @pkt_cnt: the packet number of pkt_list
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* @pkt_list: see structure rtw_pkt_buf_list
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* @cache: see enum cache_addr_type
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* @txfb: tx feedback context
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* @lat_sen: latency sensitive pkt, in lps, we will extend more awake time to rx rsp pkt.
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* Note, this structure are visible to core, phl and hal layer
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*/
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struct rtw_xmit_req {
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_os_list list;
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void *os_priv;
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enum rtw_treq_type treq_type;
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struct rtw_t_meta_data mdata;
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u32 tx_time;
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u8 shortcut_id;
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u32 total_len;
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u8 pkt_cnt;
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u8 *pkt_list;
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struct tx_local_buf *local_buf;
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struct rtw_txfb_t *txfb;
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bool lat_sen;
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#ifdef CONFIG_PHL_TX_DBG
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struct rtw_tx_dbg tx_dbg;
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#endif /* CONFIG_PHL_TX_DBG */
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#ifdef CONFIG_VW_REFINE
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u8 vw_cnt; /* total count for veriwave data */
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u8 is_map; /* whether data is pci mapped */
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#endif
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u8 role_id; /* Indicate which role is the req belongs to */
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#ifdef CONFIG_RTW_TX_HW_HDR_CONV
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u8 hw_hdr_conv;
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#endif
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enum cache_addr_type cache;
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};
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/**
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* the recv packet to core layer, store in recv phl ring
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* @os_priv: the private context from core layer
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* @mdata: see structure rtw_r_meta_data
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* @shortcut_id: short cut id this packet will use in phl/hal
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* @pkt_cnt: the packet counts of pkt_list
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* @rx_role: the role to which the RX packet is targeted
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* @tx_sta: the phl sta that sends this packet
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* @pkt_list: see structure rtw_pkt_buf_list
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*
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* Note, this structure are visible to core, phl and hal layer
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*/
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struct rtw_recv_pkt {
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void *os_priv;
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struct rtw_r_meta_data mdata;
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u8 shortcut_id;
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u8 pkt_cnt;
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u16 os_netbuf_len;
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struct rtw_wifi_role_t *rx_role;
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struct rtw_wifi_role_link_t *rx_rlink;
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struct rtw_phl_stainfo_t *tx_sta;
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struct rtw_pkt_buf_list pkt_list[MAX_RX_BUF_SEG_NUM];
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struct rtw_phl_ppdu_phy_info phy_info;
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};
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/**
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* the phl ring which stores XMIT requests can be access by both
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* core and phl, and all the requests in this ring have the same TID value
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* @cat: the category of this phl ring
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* @dma_ch: dma channel of this phl ring, query by rtw_hal_tx_chnl_mapping()
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* @tx_thres: tx threshold of this phl ring for batch handling tx requests
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* @core_idx: record the index of latest entry accessed by core layer
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* @phl_idx: record the index of handling done by phl layer
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* @phl_next_idx: record the index of latest entry accessed by phl layer
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* @entry: store the pointer of requests assigned to this phl ring
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*/
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struct rtw_phl_tx_ring {
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enum rtw_phl_ring_cat cat;
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u8 dma_ch;
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u16 tx_thres;
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u16 core_idx;
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_os_atomic phl_idx;
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_os_atomic phl_next_idx;
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u8 **entry;/* dynamic allocation */
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};
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/**
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* this structure stores sorted tx rings having frames to tx to the same sta
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* it will change everytime _phl_check_tring_list() executed
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* @list: link to the next sta which has frames to transmit
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* @sleep: true if this macid is under power-saving mode
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* @has_mgnt: true if this macid has management frames to transmit
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* @has_hiq: true if this macid has hiq frames to transmit
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* @sorted_ring: pre-sorted phl ring status list of this macid
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*/
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struct phl_tx_plan {
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_os_list list;
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bool sleep;
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bool has_mgnt;
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bool has_hiq;
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_os_list sorted_ring;
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};
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/**
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* this phl ring list contains a list of phl TX rings that have the same macid
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* and different tid, and it can be access by both core and phl
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* @list: link to next phl ring list with other macid
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* @macid: the MACID value of this phl ring list
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* @band: band of this phl ring list, band idx 0~1
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* @wmm: wmm of this phl ring list, wmm idx 0~1
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* @port: port of this phl ring list, port idx 0~4
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* @mbssid: TODO
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* @phl_ring: the phl rings with same macid but different tid, see rtw_phl_tx_ring
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* @tx_plan: transmission plan for this macid, decide by _phl_check_tring_list()
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*/
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struct rtw_phl_tring_list {
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_os_list list;
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u16 macid;
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u8 band;/*0 or 1*/
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u8 wmm;/*0 or 1*/
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u8 port;
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/*u8 mbssid*/
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struct rtw_phl_tx_ring phl_ring[MAX_PHL_RING_CAT_NUM];/* tid 0~7, 8:mgnt, 9:hiq */
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struct phl_tx_plan tx_plan;
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};
|
|
/**
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* this phl RX ring can be access by both core and phl
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* @core_idx: record the index of latest entry accessed by core layer
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* @phl_idx: record the index of handling done by phl layer
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* @entry: store the pointer of requests assigned to this phl ring
|
*/
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struct rtw_phl_rx_ring {
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_os_atomic core_idx;
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_os_atomic phl_idx;
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struct rtw_recv_pkt *entry[MAX_PHL_RX_RING_ENTRY_NUM];/* change to dynamic allocation */
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};
|
|
|
/**
|
* the physical address list
|
*/
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struct rtw_phy_addr_list {
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_os_list list;
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u32 phy_addr_l;
|
u32 phy_addr_h;
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};
|
|
/**
|
* the phl pkt tx request from phl layer to hal layer
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* @wd_page: the buffer of wd page allocated by phl and filled by hal
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* @wd_len: the len of wd page
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* @wd_seq_offset: the phl tx shortcut cached wd_page before wd_seq_offset if wd_seq_offset = 0 means no phl txsc
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* @wp_seq: pcie only, wp sequence of this phl packet request
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* @tx_req: see struct rtw_xmit_req
|
*
|
* Note, this structure should be visible to phl and hal layer (hana_todo)
|
*/
|
struct rtw_phl_pkt_req {
|
u8 *wd_page;
|
u8 wd_len;
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#ifdef CONFIG_PHL_TXSC
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u8 wd_seq_offset;
|
#endif
|
u16 wp_seq;
|
struct rtw_xmit_req *tx_req;
|
};
|
|
/*
|
0000: WIFI packet
|
0001: PPDU status
|
0010: channel info
|
0011: BB scope mode
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0100: F2P TX CMD report
|
0101: SS2FW report
|
0110: TX report
|
0111: TX payload release to host
|
1000: DFS report
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1001: TX payload release to WLCPU
|
1010: C2H packet */
|
enum rtw_rx_type {
|
RTW_RX_TYPE_WIFI = 0,
|
RTW_RX_TYPE_PPDU_STATUS = 1,
|
RTW_RX_TYPE_CHANNEL_INFO = 2,
|
RTW_RX_TYPE_TX_RPT = 3,
|
RTW_RX_TYPE_TX_WP_RELEASE_HOST = 4,
|
RTW_RX_TYPE_DFS_RPT = 5,
|
RTW_RX_TYPE_C2H = 6,
|
RTW_RX_TYPE_MAX = 0xFF
|
};
|
|
struct rtw_phl_rx_pkt {
|
_os_list list;
|
enum rtw_rx_type type;
|
u8 *rxbuf_ptr;
|
struct rtw_recv_pkt r;
|
};
|
|
|
struct rtw_xmit_recycle {
|
u16 wp_seq;
|
struct rtw_xmit_req *tx_req;
|
};
|
|
enum rtw_traffic_dir {
|
TRAFFIC_UL = 0, /* Uplink */
|
TRAFFIC_DL, /* Downlink */
|
TRAFFIC_BALANCE,
|
TRAFFIC_MAX
|
};
|
|
enum rtw_rx_fltr_opt_mode {
|
RX_FLTR_OPT_MODE_SNIFFER, /* 0 */
|
RX_FLTR_OPT_MODE_SCAN,
|
RX_FLTR_OPT_MODE_STA_LINKING,
|
RX_FLTR_OPT_MODE_STA_NORMAL,
|
RX_FLTR_OPT_MODE_AP_NORMAL,
|
RX_FLTR_OPT_MODE_LSN_DISCOV,
|
#ifdef CONFIG_PHL_TEST_MP
|
RX_FLTR_OPT_MODE_MP,
|
#endif
|
RX_FLTR_OPT_MODE_RESTORE = 0xFF
|
};
|
|
#endif /* __PHL_TRX_DEF_H_ */
|
