/******************************************************************************
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*
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* Copyright(c) 2021 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _PHL_DM_H_
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#define _PHL_DM_H_
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#ifdef CONFIG_PCI_HCI
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#ifdef RTW_WKARD_DYNAMIC_LTR
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enum rtw_phl_status
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phl_ltr_sw_trigger(struct rtw_phl_com_t *phl_com, void *hal,
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enum rtw_pcie_ltr_state state);
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enum rtw_phl_status
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phl_ltr_sw_ctrl(struct rtw_phl_com_t *phl_com, void *hal, bool enable);
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void
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phl_ltr_hw_ctrl(struct rtw_phl_com_t *phl_com, bool enable);
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void phl_ltr_sw_ctrl_ntfy(struct rtw_phl_com_t *phl_com, bool enable);
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u8 phl_ltr_get_cur_state(struct rtw_phl_com_t *phl_com);
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u32 phl_ltr_get_last_trigger_time(struct rtw_phl_com_t *phl_com);
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u32 phl_ltr_get_tri_cnt(struct rtw_phl_com_t *phl_com,
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enum rtw_pcie_ltr_state state);
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void phl_ltr_ctrl_watchdog(struct phl_info_t *phl_info);
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#endif
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#endif
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enum rtw_phl_status
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phl_edcca_cfg(struct phl_info_t *phl_info);
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enum rtw_phl_status
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phl_cmd_edcca_cfg_hdl(struct phl_info_t *phl_info, u8 *param);
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enum rtw_phl_status
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rtw_phl_cmd_edcca_mode_cfg(void *phl,
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enum rtw_edcca_mode mode,
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enum phl_cmd_type cmd_type,
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u32 cmd_timeout);
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#endif /*_PHL_DM_H_*/
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