/******************************************************************************
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*
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* Copyright(c) 2019 - 2023 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _PHL_CONFIG_H_
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#define _PHL_CONFIG_H_
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/* Define correspoding PHL Feature based on information from the Core */
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#ifdef PHL_PLATFORM_AP
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#define PHL_FEATURE_AP
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#elif defined(PHL_PLATFORM_LINUX) || defined(PHL_PLATFORM_WINDOWS) || defined(PHL_PLATFORM_UEFI)
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#define PHL_FEATURE_NIC
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#else
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#define PHL_FEATURE_NONE
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#endif
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/******************* PLATFORM Section **************************/
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#ifdef PHL_FEATURE_NONE/* enable compile flag for phl only compilation check */
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#define CONFIG_DFS 1
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#ifdef CONFIG_USB_HCI
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#define CONFIG_USB_TX_AGGREGATION
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#define CONFIG_USB_RX_AGGREGATION
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#define CONFIG_USB_TX_PADDING_CHK
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#endif
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#define CONFIG_LOAD_PHY_PARA_FROM_FILE
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#define CONFIG_WOW
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#define CONFIG_WPA3_SUITEB_SUPPORT
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#define CONFIG_SYNC_INTERRUPT
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#define CONFIG_MR_SUPPORT
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#ifdef CONFIG_MR_SUPPORT
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#if !defined(PHL_PLATFORM_LINUX_FREESTANDING)
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#define CONFIG_DBCC_SUPPORT
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#endif
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#define DBG_PHL_CHAN
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#define DBG_PHL_MR
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#define PHL_MR_PROC_CMD
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#define DBG_CHCTX_RMAP
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#endif /*CONFIG_MR_SUPPORT*/
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#if defined(CONFIG_MR_SUPPORT) || defined(CONFIG_BTCOEX)
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#define CONFIG_MR_COEX_SUPPORT
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#endif /* CONFIG_MR_SUPPORT || CONFIG_BTCOEX */
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#ifdef CONFIG_MR_COEX_SUPPORT
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#define CONFIG_MCC_SUPPORT
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#ifdef CONFIG_MCC_SUPPORT
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#define MCC_ROLE_NUM 2
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#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
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#define RTW_WKARD_HALRF_MCC
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#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
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#endif /*CONFIG_MCC_SUPPORT*/
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#endif/* CONFIG_MR_COEX_SUPPORT */
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#define DBG_PHL_MAC_REG_RW
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#define CONFIG_RTW_ACS
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#define CONFIG_RX_PSTS_PER_PKT
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#define CONFIG_PHL_TXSC
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#define CONFIG_RTW_TXSC_USE_HW_SEQ
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#define DEBUG_PHL_TX
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#define PHL_RXSC_AMPDU
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#define RTW_PHL_BCN
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#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
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#define CONFIG_PHL_TWT
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#define CONFIG_CMD_DISP
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#ifdef CONFIG_CMD_DISP
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#define CONFIG_PHL_ECSA
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/*#define CONFIG_CMD_DISP_SOLO_MODE*/
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#define CONFIG_PHL_CMD_SCAN
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#define CONFIG_PHL_CMD_SER
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#define CONFIG_PHL_CMD_BTC
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#define CONFIG_PHL_CMD_BF
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#endif
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#ifdef CONFIG_PCI_HCI
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#define PCIE_TRX_MIT_EN
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#define PHL_RXSC_ISR
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#define CONFIG_RTW_MULTI_DEV_MULTI_BAND
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#endif
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#define DEBUG_PHL_RX
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#define CONFIG_PHL_P2PPS
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#define RTW_WKARD_BFEE_SET_AID
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#define CONFIG_PHL_THERMAL_PROTECT
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#define CONFIG_PHL_TX_DBG
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#define CONFIG_PHL_SNIFFER_SUPPORT
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#define CONFIG_PHL_RELEASE_RPT_ENABLE
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#define PHL_WATCHDOG_REFINE
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#define CONFIG_PHL_DRV_HAS_NVM
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#define CONFIG_RTW_OS_HANDLER_EXT
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#define CONFIG_RTW_DEBUG_BCN_TX
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#define CONFIG_RTW_SUPPORT_MBSSID_VAP
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#define CONFIG_LIMITED_VAP_NUM (3)
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#define CONFIG_PHL_FW_DUMP_EFUSE
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#define CONFIG_PHL_CHANNEL_INFO
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#ifdef CONFIG_PHL_CHANNEL_INFO
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#define CONFIG_PHL_WKARD_CHANNEL_INFO_ACK
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#endif
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#define CONFIG_PHL_NAN
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#define CONFIG_PHL_DIAGNOSE
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#endif /* PHL_FEATURE_NONE */
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#ifdef PHL_PLATFORM_WINDOWS
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#ifndef CONFIG_CMD_DISP
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#define CONFIG_CMD_DISP
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#endif
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#define DRV_BB_CNSL_CMN_INFO
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#define CONFIG_SMART_ANTENNA
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#ifndef RTW_WD_PAGE_USE_SHMEM_POOL
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#define RTW_WD_PAGE_USE_SHMEM_POOL
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#endif
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#ifdef CONFIG_POWER_SAVE
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#define CONFIG_HW_RADIO_ONOFF_DETECT
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#endif
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#define DBG_DUMP_CMAC_CFG_INFO
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#define CONFIG_BTCOEX
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#endif
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#ifdef PHL_PLATFORM_LINUX
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#ifdef CONFIG_PCI_HCI
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/* Driver needs to handle cache-memory coherence for DMA */
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#ifndef CONFIG_RTW_DMA_IS_COHERENT
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#define PHL_DMA_NONCOHERENT
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#endif
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/* DMA is IOMMU. map/unmap must be paired, including size */
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#ifdef CONFIG_RTW_UNPAIRED_DMA_MAP_UNMAP
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#define PHL_UNPAIRED_DMA_MAP_UNMAP
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#endif
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/* DMA address is 64-bit */
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#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
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#define PHL_DMA_ADDR_64
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#endif
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#endif /* CONFIG_PCI_HCI */
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/* comment out cfg temporarily */
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/*
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#define CONFIG_FSM
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#ifndef CONFIG_FSM
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#define CONFIG_CMD_DISP
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#endif
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*/
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#define CONFIG_BTCOEX
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#define DEBUG_PHL_RX
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#endif
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#ifdef PHL_PLATFORM_UEFI
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#ifndef CONFIG_CMD_DISP
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#define CONFIG_CMD_DISP
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#endif
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#define RTW_WKARD_REDUCE_GET_TIME_USAGE
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#define CONFIG_RX_PSTS_PER_PKT
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#endif
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/******************* Feature flags **************************/
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#define MAC_PHL_TEMP_CROSS_DEFINE
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#ifdef CONFIG_PHL_TEST_SUITE
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#define CONFIG_PHL_TEST_MP
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#define CONFIG_PHL_TEST_VERIFY
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#endif
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#ifdef CONFIG_CORE_SYNC_INTERRUPT
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#define CONFIG_SYNC_INTERRUPT
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#endif
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/* #define CONFIG_PHL_IO_OFLD */
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#define CONFIG_PHL_SCANOFLD
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#define CONFIG_PHL_CHSWOFLD
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#ifdef CONFIG_WOW
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#define CONFIG_WOWLAN
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/* #define RTW_WKARD_WOW_SKIP_AOAC_RPT */
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/* #define RTW_WKARD_WOW_SKIP_WOW_CAM_CONFIG */
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#define RTW_WKARD_WOW_L2_PWR
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#define DBG_RST_BDRAM_TIME
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#ifndef CONFIG_PHL_SCANOFLD
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#define CONFIG_PHL_SCANOFLD
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#endif
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#endif
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#define DBG_PHY_ON_TIME
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/*CONFIG_IFACE_NUMBER*/
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#ifdef CONFIG_IFACE_NUMBER
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#define MAX_WIFI_ROLE_NUMBER CONFIG_IFACE_NUMBER
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#else
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#define MAX_WIFI_ROLE_NUMBER 5
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#endif
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#if defined(CONFIG_RTW_SUPPORT_MBSSID_VAP) && defined(CONFIG_LIMITED_VAP_NUM)
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#define MAX_MBSSID_NUMBER (CONFIG_LIMITED_VAP_NUM)
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#else
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#define MAX_MBSSID_NUMBER (0)
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#endif /* CONFIG_RTW_SUPPORT_MBSSID_VAP */
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#ifdef CONFIG_CONCURRENT_MODE
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#define CONFIG_MR_SUPPORT
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#endif
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#ifdef CONFIG_REUSED_FWDL_BUF
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#define CONFIG_PHL_REUSED_FWDL_BUF
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#endif
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#ifdef CONFIG_MR_SUPPORT
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/*#define CONFIG_DBCC_SUPPORT*/
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#ifdef CONFIG_DBCC_SUPPORT
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/*#define DBG_DBCC_MONITOR_TIME*/
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#ifdef DBG_DBCC_MONITOR_TIME
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#define DBG_MONITOR_TIME
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#endif
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#endif
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#define DBG_PHL_CHAN
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#define DBG_PHL_MR
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#define PHL_MR_PROC_CMD
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#define DBG_CHCTX_RMAP
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#endif
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#if defined(CONFIG_MR_SUPPORT) || defined(CONFIG_BTCOEX)
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#define CONFIG_MR_COEX_SUPPORT
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#endif /* CONFIG_MR_SUPPORT || CONFIG_BTCOEX */
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#ifdef CONFIG_MR_COEX_SUPPORT
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#define CONFIG_MCC_SUPPORT
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#ifdef CONFIG_MCC_SUPPORT
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#define MCC_ROLE_NUM 2
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#define RTW_WKARD_GO_BT_TS_ADJUST_VIA_NOA
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#define RTW_WKARD_HALRF_MCC
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#define RTW_WKARD_TDMRA_AUTO_GET_STAY_ROLE
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#endif /*CONFIG_MCC_SUPPORT*/
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#endif /* CONFIG_MR_COEX_SUPPORT */
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#define DBG_PHL_STAINFO
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#define PHL_MAX_STA_NUM 128
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#define PHL_MAX_MLD_NUM (PHL_MAX_STA_NUM)
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/**** CONFIG_CMD_DISP ***/
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#ifdef DISABLE_CMD_DISPR
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#undef CONFIG_CMD_DISP
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#endif
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#ifdef CONFIG_CMD_DISP
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/* enable SOLO mode define to create seperated background thread per dispatcher,
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* otherwise, all dispatcher would share single background thread, which is in share mode.
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*/
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/*#define CONFIG_CMD_DISP_SOLO_MODE*/
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/* Enable Self-Defined Sequence feature for sender to rearrange dispatch order,
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* Since this is not a mandatory feature and would have addiional memory cost (arround 2200 Bytes)
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* Disable by default.
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*/
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/*#define CONFIG_CMD_DISP_SUPPORT_CUSTOM_SEQ*/
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#define CONFIG_PHL_CMD_SCAN
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#ifdef CONFIG_CMD_SER
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#define CONFIG_PHL_CMD_SER
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#endif
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#define CONFIG_PHL_CMD_BF
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#ifdef CONFIG_MSG_NUM
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#define CONFIG_PHL_MSG_NUM CONFIG_MSG_NUM
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#endif
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#endif /**** CONFIG_CMD_DISP ***/
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#define CONFIG_GEN_GIT_INFO 1
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/*#define CONFIG_NEW_HALMAC_INTERFACE*/
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/* AP mode & UEFI not suppot BTC currently */
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#ifdef CONFIG_BTCOEX
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#define CONFIG_PHL_CMD_BTC
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#endif
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#ifdef CONFIG_USB_TX_PADDING_CHK
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#define CONFIG_PHL_USB_TX_PADDING_CHK
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#endif
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#ifdef CONFIG_USB_TX_AGGREGATION
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#define CONFIG_PHL_USB_TX_AGGREGATION
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#endif
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#ifdef CONFIG_USB_RX_AGGREGATION
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#define CONFIG_PHL_USB_RX_AGGREGATION
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#endif
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#if CONFIG_DFS
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#define CONFIG_PHL_DFS_SWITCH_CH_WITH_CSA
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#ifdef CONFIG_DFS_MASTER
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#define CONFIG_PHL_DFS
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#endif
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#endif
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#ifdef CONFIG_WPP
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#define CONFIG_PHL_WPP
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#endif
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#ifdef CONFIG_TCP_CSUM_OFFLOAD_TX
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#define CONFIG_PHL_CSUM_OFFLOAD_TX
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#endif
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#ifdef CONFIG_TCP_CSUM_OFFLOAD_RX
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#define CONFIG_PHL_CSUM_OFFLOAD_RX
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#endif
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#ifdef CONFIG_RX_PSTS_PER_PKT
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#define CONFIG_PHL_RX_PSTS_PER_PKT
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#ifndef CONFIG_SNIFFER_SUPPORT
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#define RTW_WKARD_DISABLE_PSTS_PER_PKT_DATA
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#endif
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#endif
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#ifdef CONFIG_SDIO_RX_NETBUF_ALLOC_IN_PHL
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#define CONFIG_PHL_SDIO_RX_NETBUF_ALLOC_IN_PHL
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#endif
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#ifdef CONFIG_SDIO_READ_RXFF_IN_INT
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#define CONFIG_PHL_SDIO_READ_RXFF_IN_INT
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#endif
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#ifdef CONFIG_ECSA
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#define CONFIG_PHL_ECSA
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#ifdef CONFIG_ECSA_EXTEND_OPTION
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#define CONFIG_PHL_ECSA_EXTEND_OPTION
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#endif
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#endif
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#ifdef CONFIG_TWT
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#define CONFIG_PHL_TWT
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#endif
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#ifdef CONFIG_NAN
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#define CONFIG_PHL_NAN
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#endif
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#ifdef CONFIG_RA_TXSTS_DBG
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#define CONFIG_PHL_RA_TXSTS_DBG
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#endif
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#ifdef CONFIG_RELEASE_RPT
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#define CONFIG_PHL_RELEASE_RPT_ENABLE
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#endif
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#ifdef CONFIG_PS_FW_DBG
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#define CONFIG_PHL_PS_FW_DBG
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#endif
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#ifdef CONFIG_P2PPS
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#define CONFIG_PHL_P2PPS
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#endif
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#ifdef CONFIG_WD_PAGE_RESET
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#define CONFIG_PHL_WD_PAGE_RESET
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#endif
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#ifdef CONFIG_TX_DBG
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#define CONFIG_PHL_TX_DBG
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#endif
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#ifdef CONFIG_PCI_HCI
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#ifdef CONFIG_PCIE_TRX_MIT
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#define PCIE_TRX_MIT_EN
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#endif
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#endif
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#ifdef CONFIG_THERMAL_PROTECT
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#define CONFIG_PHL_THERMAL_PROTECT
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#endif
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#ifdef CONFIG_RX_BATCH_IND
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#define PHL_RX_BATCH_IND
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#endif
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#ifdef CONFIG_TDLS
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#define CONFIG_PHL_TDLS
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#endif
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#ifdef CONFIG_SDIO_HCI
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/* For SDIO TX TP TST - START */
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#ifdef CONFIG_SDIO_TX_AGG_NUM_MAX
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#define PHL_SDIO_TX_AGG_MAX CONFIG_SDIO_TX_AGG_NUM_MAX
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#endif /* CONFIG_SDIO_TX_AGG_NUM_MAX */
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#define CONFIG_PHL_SDIO_TX_CB_THREAD
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/*
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* RTW_WKARD_SDIO_TX_USE_YIELD
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* Define this would use yield() instead of event wait mechanism to improve
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* throughput on Linux platform.
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* But yield() doesn't been encouraged to use in Linux,
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* so if we figure out what happened and find another way to improve
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* throughput, this workaround would be removed later.
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*
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* RTW_WKARD_SDIO_TX_USE_YIELD is depended on CONFIG_PHL_SDIO_TX_CB_THREAD,
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* because the mechanism only been used with CONFIG_PHL_SDIO_TX_CB_THREAD.
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*
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* Usually this flag would be defined from core layer.
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*/
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/*#define RTW_WKARD_SDIO_TX_USE_YIELD*/
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#define SDIO_TX_THREAD /* Use dedicate thread for SDIO TX */
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/* For SDIO TX TP TST - ENDT */
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/* For SDIO RX TP TST - START */
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#define CONFIG_PHL_SDIO_RX_CB_THREAD
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/* For SDIO RX TP TST - END */
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#endif /* CONFIG_SDIO_HCI */
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#ifdef CONFIG_MAC_REG_RW_CHK
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#define DBG_PHL_MAC_REG_RW
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#endif
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#ifdef CONFIG_RTW_DRV_HAS_NVM
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/* Driver has it's own NVM to store MP calibration values
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* and system configuration instead of efuse. */
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#define CONFIG_PHL_DRV_HAS_NVM
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#endif /* CONFIG_RTW_DRV_HAS_NVM */
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#ifdef CONFIG_PCI_TRX_RES_DBG
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#define CONFIG_PHL_PCI_TRX_RES_DBG
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#endif
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#ifdef CONFIG_ACS
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#define CONFIG_RTW_ACS
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#endif
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#ifdef CONFIG_SNIFFER_SUPPORT
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#define CONFIG_PHL_SNIFFER_SUPPORT
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#endif
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#ifdef CONFIG_RTW_CSI_CHANNEL_INFO
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#define CONFIG_PHL_CHANNEL_INFO /*WiFi Sensing*/
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#ifdef CONFIG_PHL_CHANNEL_INFO
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#define CONFIG_PHL_WKARD_CHANNEL_INFO_ACK
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#define CONFIG_PHL_WKARD_CHANNEL_INFO_SAP
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#endif
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#define CONFIG_PHL_CHANNEL_INFO_DBG
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#endif
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#ifdef CONFIG_FW_DUMP_EFUSE
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#define CONFIG_PHL_FW_DUMP_EFUSE
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#endif
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#ifdef CONFIG_PHL_WACHDOG_REFINE
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#define PHL_WATCHDOG_REFINE
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#endif
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#ifdef DIAGNOSTIC_ANALYTICS
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#define CONFIG_PHL_DIAGNOSE
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#endif
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#ifdef CONFIG_NARROWBAND_SUPPORTING
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#define CONFIG_PHL_NARROW_BW
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#endif /*CONFIG_NARROWBAND_SUPPORTING*/
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/**** FPGA mode ****/
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/* #define FPGA_TEST */
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#ifdef FPGA_TEST
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#undef CONFIG_BTCOEX
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#undef USE_TRUE_PHY
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#endif
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/******************* WKARD flags **************************/
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#define RTW_WKARD_P2PPS_REFINE
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#define RTW_WKARD_P2PPS_SINGLE_NOA
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#define RTW_WKARD_P2PPS_NOA_MCC
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#ifdef PHL_PLATFORM_LINUX
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#define RTW_WKARD_RF_CR_DUMP
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#define RTW_WKARD_LINUX_CMD_WKARD
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#endif
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#ifdef PHL_PLATFORM_WINDOWS
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/* Workaround for doing hal reset in changing MP mode will lost the mac entry */
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#define RTW_WKARD_MP_MODE_CHANGE
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#define RTW_WKARD_WIN_TRX_BALANCE
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#define RTW_WKARD_DYNAMIC_LTR
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#endif
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#ifdef PHL_PLATFORM_AP
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#define RTW_WKARD_98D_INTR_EN_TIMING
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#define RTW_WKARD_AP_MP
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#endif
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#define RTW_WKARD_PHY_CAP
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#define RTW_WKARD_BTC_STBC_CAP
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#define RTW_WKARD_LAMODE
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#define RTW_WKARD_TXSC
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#define RTW_WKARD_BB_C2H
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#define RTW_WKARD_STA_BCN_INTERVAL
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#define RTW_WKARD_SER_L1_EXPIRE
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#define RTW_WKARD_RESET_LPS_STS
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#ifdef CONFIG_USB_HCI
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#define RTW_WKARD_SER_USB_POLLING_EVENT
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#endif
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#ifdef CONFIG_RX_BUFF_NONCACHE_ADDR
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#ifdef CONFIG_DYNAMIC_RX_BUF
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#undef CONFIG_DYNAMIC_RX_BUF
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#endif
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#endif
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/* #define RTW_WKARD_SER_USB_DISABLE_L1_RCVY_FLOW */
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#define RTW_WKARD_BTC_RFETYPE
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#define RTW_WKARD_TXBD_UPD_LMT /* 8852AE/8852BE txbd index update limitation */
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#ifdef CONFIG_WPA3_SUITEB_SUPPORT
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#define RTW_WKARD_HW_MGNT_GCMP_256_DISABLE
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#endif
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/* Workaround for cmac table config
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* - Default is disabled until halbb is ready
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* - This workaround will be removed once fw handles this cfg
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*/
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/*#define RTW_WKARD_DEF_CMACTBL_CFG*/
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/* Workaround for cmac table config
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* - This workaround will be removed once fw handles this cfg
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*/
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#define RTW_WKARD_DEF_CMACTBL_CFG
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#define RTW_WKARD_USB_TXAGG_BULK_END_WD
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#ifdef CONFIG_HOMOLOGATION
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#define CONFIG_PHL_HOMOLOGATION
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#endif
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#ifdef RTW_WKARD_TX_DISABLE_BFEE
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#define RTW_WKARD_DYNAMIC_BFEE_CAP
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#endif
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#ifdef RTW_WKARD_NTFY_MEDIA_STS
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#define RTW_WKARD_PHL_NTFY_MEDIA_STS
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#endif
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#ifdef PHL_PLATFORM_WINDOWS
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#define CONFIG_WOW_WITH_SER
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#endif
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#ifdef PHL_PLATFORM_WINDOWS
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#define CONFIG_PHL_PATH_DIV
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#endif
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/*
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* Workaround for phl_mr_offch_hdl sleep after issue null data,
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* - This workaround will be removed once tx report is ready
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*/
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#ifndef RTW_WKARD_TX_NULL_WD_RP
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#define RTW_WKARD_ISSUE_NULL_SLEEP_PROTECTION
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#endif
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#ifdef RTW_WKARD_LPS_IQK_TWICE
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#define RTW_WKARD_PHL_LPS_IQK_TWICE
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#endif
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#define RTW_WKARD_BUSCAP_IN_HALSPEC
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#define RTW_WKARD_IBSS_SNIFFER_MODE
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#define RTW_WKARD_SINGLE_PATH_RSSI
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#define RTW_WKARD_BFEE_DISABLE_NG16
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#define RTW_WKARD_HW_WMM_ALLOCATE
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#ifdef RTW_WKARD_BFEE_AID
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#define RTW_WKARD_BFEE_SET_AID
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#endif
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#ifdef RTW_WKARD_TRIGGER_FRAME_PARSER
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#define RTW_WKARD_RX_FLTR_HE_TF
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#endif
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#define RTW_WKARD_PHY_RPT_CCK_CH_IDX
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#ifdef RTW_WKARD_DISABLE_2G40M_ULOFDMA
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#define RTW_WKARD_BB_DISABLE_STA_2G40M_ULOFDMA
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#endif
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#define RTW_WKARD_WPOFFSET
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#ifdef PHL_PLATFORM_LINUX
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#define RTW_TX_COALESCE_BAK_PKT_LIST
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#endif
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#define RTW_WKARD_MU_PPDU_STS_RX_RATE
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#ifdef PHL_PLATFORM_WINDOWS
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#define CONFIG_DIG_TDMA
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#endif
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/* DCM might have some IOT issue, please see PCIE-9556 */
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#define RTW_WKARD_DISABLE_DCM
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#endif /*_PHL_CONFIG_H_*/
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