/******************************************************************************
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*
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* Copyright(c) 2016 - 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#define _RTL8852BE_HALINIT_C_
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#include "../rtl8852b_hal.h"
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#include "hal_trx_8852be.h"
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static enum mac_ax_pcie_func_ctrl
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_hal_set_each_pcicfg(enum rtw_pcie_bus_func_cap_t ctrl)
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{
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switch(ctrl) {
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case RTW_PCIE_BUS_FUNC_DISABLE:
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return MAC_AX_PCIE_DISABLE;
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case RTW_PCIE_BUS_FUNC_ENABLE:
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return MAC_AX_PCIE_ENABLE;
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default:
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return MAC_AX_PCIE_DEFAULT;
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}
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}
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static enum rtw_pcie_bus_func_cap_t
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_trans_func_ctrl(enum mac_ax_pcie_func_ctrl ctrl)
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{
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switch (ctrl) {
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case MAC_AX_PCIE_DISABLE:
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return RTW_PCIE_BUS_FUNC_DISABLE;
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case MAC_AX_PCIE_ENABLE:
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return RTW_PCIE_BUS_FUNC_ENABLE;
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case MAC_AX_PCIE_DEFAULT:
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return RTW_PCIE_BUS_FUNC_DEFAULT;
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case MAC_AX_PCIE_IGNORE:
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return RTW_PCIE_BUS_FUNC_IGNORE;
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default:
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PHL_ERR("%s : unknown\n", __func__);
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return RTW_PCIE_BUS_FUNC_IGNORE;
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}
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}
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#define case_mac_ax_pcie_dly(src) \
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case MAC_AX_PCIE_##src: return RTW_PHL_PCIE_##src
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static u8 _trans_l0sdly(enum mac_ax_pcie_l0sdly val)
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{
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switch (val) {
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case_mac_ax_pcie_dly(L0SDLY_1US);
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case_mac_ax_pcie_dly(L0SDLY_2US);
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case_mac_ax_pcie_dly(L0SDLY_3US);
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case_mac_ax_pcie_dly(L0SDLY_4US);
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case_mac_ax_pcie_dly(L0SDLY_5US);
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case_mac_ax_pcie_dly(L0SDLY_6US);
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case_mac_ax_pcie_dly(L0SDLY_7US);
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case_mac_ax_pcie_dly(L0SDLY_R_ERR);
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case_mac_ax_pcie_dly(L0SDLY_DEF);
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case_mac_ax_pcie_dly(L0SDLY_IGNORE);
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default:
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return val;
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};
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}
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static u8 _trans_l1dly(enum mac_ax_pcie_l1dly val)
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{
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switch (val) {
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case_mac_ax_pcie_dly(L1DLY_16US);
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case_mac_ax_pcie_dly(L1DLY_32US);
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case_mac_ax_pcie_dly(L1DLY_64US);
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case_mac_ax_pcie_dly(L1DLY_INFI);
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case_mac_ax_pcie_dly(L1DLY_R_ERR);
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case_mac_ax_pcie_dly(L1DLY_DEF);
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case_mac_ax_pcie_dly(L1DLY_IGNORE);
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default:
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return val;
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};
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};
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static u8 _trans_clkdly(enum mac_ax_pcie_clkdly val)
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{
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switch (val) {
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case_mac_ax_pcie_dly(CLKDLY_0);
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case_mac_ax_pcie_dly(CLKDLY_5US);
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case_mac_ax_pcie_dly(CLKDLY_6US);
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case_mac_ax_pcie_dly(CLKDLY_11US);
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case_mac_ax_pcie_dly(CLKDLY_15US);
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case_mac_ax_pcie_dly(CLKDLY_19US);
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case_mac_ax_pcie_dly(CLKDLY_25US);
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case_mac_ax_pcie_dly(CLKDLY_30US);
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case_mac_ax_pcie_dly(CLKDLY_38US);
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case_mac_ax_pcie_dly(CLKDLY_50US);
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case_mac_ax_pcie_dly(CLKDLY_64US);
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case_mac_ax_pcie_dly(CLKDLY_100US);
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case_mac_ax_pcie_dly(CLKDLY_128US);
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case_mac_ax_pcie_dly(CLKDLY_150US);
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case_mac_ax_pcie_dly(CLKDLY_192US);
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case_mac_ax_pcie_dly(CLKDLY_200US);
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case_mac_ax_pcie_dly(CLKDLY_300US);
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case_mac_ax_pcie_dly(CLKDLY_400US);
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case_mac_ax_pcie_dly(CLKDLY_500US);
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case_mac_ax_pcie_dly(CLKDLY_1MS);
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case_mac_ax_pcie_dly(CLKDLY_3MS);
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case_mac_ax_pcie_dly(CLKDLY_5MS);
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case_mac_ax_pcie_dly(CLKDLY_10MS);
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case_mac_ax_pcie_dly(CLKDLY_R_ERR);
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case_mac_ax_pcie_dly(CLKDLY_DEF);
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case_mac_ax_pcie_dly(CLKDLY_IGNORE);
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default:
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return val;
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};
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}
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static enum rtw_hal_status _hal_aspm_disable_8852be(struct hal_info_t *hal_info)
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{
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struct mac_ax_pcie_cfgspc_param pcicfg;
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enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
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_os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
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pcicfg.write = 1;
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/* set disable to l0s l1 l1ss */
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pcicfg.l0s_ctrl = MAC_AX_PCIE_DISABLE;
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pcicfg.l1_ctrl = MAC_AX_PCIE_DISABLE;
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pcicfg.l1ss_ctrl = MAC_AX_PCIE_DISABLE;
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/* set ignore to others */
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pcicfg.wake_ctrl = MAC_AX_PCIE_IGNORE;
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pcicfg.crq_ctrl = MAC_AX_PCIE_IGNORE;
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pcicfg.clkdly_ctrl = MAC_AX_PCIE_IGNORE;
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pcicfg.l0sdly_ctrl = MAC_AX_PCIE_IGNORE;
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pcicfg.l1dly_ctrl = MAC_AX_PCIE_IGNORE;
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
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"%s : l0s/l1/l1ss/wake/crq/l0sdly/l1dly/clkdly = %#X/%#X/%#X/%#X/%#X/%#X/%#X/%#X \n",
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__func__, pcicfg.l0s_ctrl, pcicfg.l1_ctrl, pcicfg.l1ss_ctrl, pcicfg.wake_ctrl,
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pcicfg.crq_ctrl, pcicfg.l0sdly_ctrl, pcicfg.l1dly_ctrl, pcicfg.clkdly_ctrl);
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hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
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return hsts;
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}
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enum rtw_hal_status
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hal_get_pcicfg_8852be(struct hal_info_t *hal_info,
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struct rtw_pcie_cfgspc_param *cfg)
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{
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enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
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struct mac_ax_pcie_cfgspc_param pcicfg = {0};
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_os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
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pcicfg.read = 1;
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hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
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if (hsts != RTW_HAL_STATUS_SUCCESS) {
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PHL_ERR("%s : status %u\n", __func__, hsts);
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return hsts;
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}
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cfg->l0s_ctrl = _trans_func_ctrl(pcicfg.l0s_ctrl);
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cfg->l1_ctrl = _trans_func_ctrl(pcicfg.l1_ctrl);
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cfg->l1ss_ctrl = _trans_func_ctrl(pcicfg.l1ss_ctrl);
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cfg->wake_ctrl = _trans_func_ctrl(pcicfg.wake_ctrl);
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cfg->crq_ctrl = _trans_func_ctrl(pcicfg.crq_ctrl);
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cfg->l0sdly = _trans_l0sdly(pcicfg.l0sdly_ctrl);
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cfg->l1dly = _trans_l1dly(pcicfg.l1dly_ctrl);
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cfg->clkdly = _trans_clkdly(pcicfg.clkdly_ctrl);
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return RTW_HAL_STATUS_SUCCESS;
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}
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enum rtw_hal_status _hal_ltr_sw_init_state_8852be(struct hal_info_t *hal_info)
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{
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enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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enum rtw_pcie_ltr_state state;
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
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"%s :sw state = %u \n",__func__, hal_com->bus_cap.ltr_init_state);
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if (hal_com->bus_cap.ltr_init_state > 0) {
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state = hal_com->bus_cap.ltr_init_state;
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hsts = rtw_hal_mac_ltr_sw_trigger(hal_info,state);
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} else {
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hsts = RTW_HAL_STATUS_SUCCESS;
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}
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return hsts;
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}
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enum rtw_hal_status _hal_ltr_set_pcie_8852be(struct hal_info_t *hal_info)
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{
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enum rtw_hal_status hsts = RTW_HAL_STATUS_SUCCESS;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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struct bus_cap_t *bus_cap = &hal_com->bus_cap;
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
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"%s :idle_ctrl/idle_val/act_ctrl/act_val = %u/%#X/%u/%#X \n",
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__func__, bus_cap->ltr_idle.ctrl,
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bus_cap->ltr_idle.val, bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
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if (bus_cap->ltr_idle.ctrl || bus_cap->ltr_act.ctrl) {
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hsts = rtw_hal_mac_ltr_set_pcie(hal_info, RTW_PCIE_BUS_FUNC_IGNORE,
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bus_cap->ltr_idle.ctrl, bus_cap->ltr_idle.val,
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bus_cap->ltr_act.ctrl, bus_cap->ltr_act.val);
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}
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return hsts;
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}
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static void _hal_aspm_hw_cfg(struct hal_info_t *hal)
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{
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struct rtw_hal_com_t *hal_com = hal->hal_com;
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/* func */
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hal_com->bus_hw_cap.l0s_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
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hal_com->bus_hw_cap.l1_ctrl = RTW_PCIE_BUS_FUNC_ENABLE;
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hal_com->bus_hw_cap.l1ss_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
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hal_com->bus_hw_cap.wake_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
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hal_com->bus_hw_cap.crq_ctrl = RTW_PCIE_BUS_FUNC_DEFAULT;
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/*delay*/
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hal_com->bus_hw_cap.l0sdly_ctrl = MAC_AX_PCIE_L0SDLY_DEF;
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hal_com->bus_hw_cap.l1dly_ctrl = MAC_AX_PCIE_L1DLY_DEF;
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hal_com->bus_hw_cap.clkdly_ctrl = MAC_AX_PCIE_CLKDLY_DEF;
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}
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static void _hal_tx_ch_config_8852be(struct hal_info_t *hal)
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{
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struct mac_ax_txdma_ch_map *txch_map = (struct mac_ax_txdma_ch_map *)hal->txch_map;
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txch_map->ch0 = MAC_AX_PCIE_ENABLE;
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txch_map->ch1 = MAC_AX_PCIE_ENABLE;
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txch_map->ch2 = MAC_AX_PCIE_ENABLE;
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txch_map->ch3 = MAC_AX_PCIE_ENABLE;
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txch_map->ch4 = MAC_AX_PCIE_DISABLE;
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txch_map->ch5 = MAC_AX_PCIE_DISABLE;
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txch_map->ch6 = MAC_AX_PCIE_DISABLE;
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txch_map->ch7 = MAC_AX_PCIE_DISABLE;
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txch_map->ch8 = MAC_AX_PCIE_ENABLE;
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txch_map->ch9 = MAC_AX_PCIE_ENABLE;
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txch_map->ch10 = MAC_AX_PCIE_DISABLE;
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txch_map->ch11 = MAC_AX_PCIE_DISABLE;
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txch_map->ch12 = MAC_AX_PCIE_ENABLE;
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}
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static void _hal_pre_init_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal_info,
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struct hal_init_info_t *init_52be)
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{
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struct mac_ax_trx_info *trx_info = &init_52be->trx_info;
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struct mac_ax_intf_info *intf_info = &init_52be->intf_info;
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struct mac_ax_host_rpr_cfg *rpr_cfg = (struct mac_ax_host_rpr_cfg *)hal_info->rpr_cfg;
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void *txbd_buf = NULL;
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void *rxbd_buf = NULL;
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/* trx_info */
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if (true == phl_com->dev_cap.tx_mu_ru)
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trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
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else
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trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
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if (phl_com->dev_cap.quota_turbo == true)
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trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
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else
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trx_info->qta_mode = MAC_AX_QTA_SCC;
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#ifdef RTW_WKARD_LAMODE
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PHL_INFO("%s : la_mode %d\n", __func__, phl_com->dev_cap.la_mode);
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if (phl_com->dev_cap.la_mode)
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trx_info->qta_mode = MAC_AX_QTA_LAMODE;
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#endif
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/* Calculate max release report aggregation number that could fit
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* into RPQ buffer */
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if (hal_info->hal_com->bus_cap.rpbuf_size) {
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s32 agg = hal_info->hal_com->bus_cap.rpbuf_size
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- RX_BD_INFO_SIZE
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- RX_DESC_S_SIZE_8852B;
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if (agg <= 0)
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PHL_ERR("RP buffer is too small!(%u)\n",
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hal_info->hal_com->bus_cap.rpbuf_size);
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agg = (agg / RX_RP_PACKET_SIZE) - 1; /* set N - 1 to agg N. */
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/* Not exceed HALMAC's default 121 */
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if (agg > 121)
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agg = 121;
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/* Use maximum number fit into RPQ if not set or set to too
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large */
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if ((phl_com->dev_cap.rpq_agg_num == 0)
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|| (phl_com->dev_cap.rpq_agg_num > (u8)agg)) {
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PHL_INFO("RP agg set to %d for %uB (orig is %u).\n",
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agg, hal_info->hal_com->bus_cap.rpbuf_size,
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phl_com->dev_cap.rpq_agg_num);
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phl_com->dev_cap.rpq_agg_num = (u8)agg;
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}
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}
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if (phl_com->dev_cap.rpq_agg_num) {
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rpr_cfg->agg_def = 0;
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rpr_cfg->agg = phl_com->dev_cap.rpq_agg_num;
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} else {
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rpr_cfg->agg_def = 1;
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}
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rpr_cfg->tmr_def = 1;
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rpr_cfg->txok_en = MAC_AX_FUNC_DEF;
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rpr_cfg->rty_lmt_en = MAC_AX_FUNC_DEF;
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rpr_cfg->lft_drop_en = MAC_AX_FUNC_DEF;
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rpr_cfg->macid_drop_en = MAC_AX_FUNC_DEF;
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trx_info->rpr_cfg = rpr_cfg;
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/* intf_info */
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txbd_buf = rtw_phl_get_txbd_buf(phl_com);
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rxbd_buf = rtw_phl_get_rxbd_buf(phl_com);
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intf_info->txbd_trunc_mode = MAC_AX_BD_TRUNC;
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intf_info->rxbd_trunc_mode = MAC_AX_BD_TRUNC;
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intf_info->rxbd_mode = MAC_AX_RXBD_PKT;
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intf_info->tag_mode = MAC_AX_TAG_MULTI;
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intf_info->tx_burst = MAC_AX_TX_BURST_DEF;
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intf_info->rx_burst = MAC_AX_RX_BURST_DEF;
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intf_info->wd_dma_idle_intvl = MAC_AX_WD_DMA_INTVL_DEF;
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intf_info->wd_dma_act_intvl = MAC_AX_WD_DMA_INTVL_DEF;
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intf_info->multi_tag_num = MAC_AX_TAG_NUM_DEF;
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intf_info->rx_sep_append_len = 0;
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intf_info->txbd_buf = txbd_buf;
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intf_info->rxbd_buf = rxbd_buf;
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intf_info->skip_all = false;
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intf_info->autok_en = MAC_AX_PCIE_DISABLE;
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intf_info->txbd_num = (u16)hal_info->hal_com->bus_cap.txbd_num;
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intf_info->rxbd_num = (u16)hal_info->hal_com->bus_cap.rxbd_num;
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intf_info->rpbd_num = (u16)hal_info->hal_com->bus_cap.rpbd_num;
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_hal_tx_ch_config_8852be(hal_info);
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intf_info->txch_map = (struct mac_ax_txdma_ch_map *)hal_info->txch_map;
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intf_info->lbc_en = MAC_AX_PCIE_DEFAULT;
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intf_info->lbc_tmr = MAC_AX_LBC_TMR_DEF;
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intf_info->io_rcy_en = MAC_AX_PCIE_DEFAULT;
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intf_info->io_rcy_tmr = MAC_AX_IO_RCY_ANA_TMR_DEF;
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/* others */
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init_52be->ic_name = "rtl8852be";
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}
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void init_hal_spec_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal)
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{
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struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
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struct rtw_hal_com_t *hal_com = hal->hal_com;
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struct bus_hw_cap_t *bus_hw_cap = &hal_com->bus_hw_cap;
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init_hal_spec_8852b(phl_com, hal);
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hal_spec->rx_bd_info_sz = RX_BD_INFO_SIZE;
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hal_spec->rx_tag[0] = 0;
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hal_spec->rx_tag[1] = 0;
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bus_hw_cap->max_txbd_num = 0x3FF;
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bus_hw_cap->max_rxbd_num = 0x3FF;
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bus_hw_cap->max_rpbd_num = 0x3FF;
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bus_hw_cap->max_rxbuf_size = RX_BUF_SIZE;
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bus_hw_cap->max_rpbuf_size = RX_BUF_SIZE;
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bus_hw_cap->max_wd_page_size = 128;
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bus_hw_cap->wdb_size = 24;
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bus_hw_cap->wdi_size = 24;
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bus_hw_cap->txbd_len = 8;
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bus_hw_cap->rxbd_len = 8;
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bus_hw_cap->addr_info_size = 8;
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bus_hw_cap->seq_info_size = 8;
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#ifdef RTW_WKARD_BUSCAP_IN_HALSPEC
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hal_spec->phyaddr_num = 8;
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#endif
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hal_spec->addr_info_len_lmt = 65535;
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phl_com->dev_cap.hw_sup_flags |= HW_SUP_PCIE_PLFH;/*PCIe payload from host*/
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_hal_aspm_hw_cfg(hal);
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if (hal_com->cv == CAV) {
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bus_hw_cap->ltr_sw_ctrl = true;
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bus_hw_cap->ltr_hw_ctrl = false;
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} else {
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bus_hw_cap->ltr_sw_ctrl = false;
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bus_hw_cap->ltr_hw_ctrl = true;
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}
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hal_com->dev_hw_cap.ps_cap.lps_pause_tx = false;
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hal_spec->ser_cfg_int = false;
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hal_spec->ps_cfg_int = false;
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}
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enum rtw_hal_status hal_get_efuse_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal_info)
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{
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struct hal_init_info_t init_52be;
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_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
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_hal_pre_init_8852be(phl_com, hal_info, &init_52be);
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return hal_get_efuse_8852b(phl_com, hal_info, &init_52be);
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}
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enum rtw_hal_status hal_set_pcicfg_8852be(struct hal_info_t *hal_info)
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{
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struct mac_ax_pcie_cfgspc_param pcicfg;
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enum rtw_hal_status hsts = RTW_HAL_STATUS_FAILURE;
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struct rtw_hal_com_t *hal_com = hal_info->hal_com;
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_os_mem_set(hal_to_drvpriv(hal_info), &pcicfg, 0, sizeof(pcicfg));
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pcicfg.write = 1;
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pcicfg.l0s_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l0s_ctrl);
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pcicfg.l1_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1_ctrl);
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pcicfg.l1ss_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.l1ss_ctrl);
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pcicfg.wake_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.wake_ctrl);
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pcicfg.crq_ctrl = _hal_set_each_pcicfg(hal_com->bus_cap.crq_ctrl);
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pcicfg.clkdly_ctrl = hal_com->bus_cap.clkdly_ctrl;
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pcicfg.l0sdly_ctrl = hal_com->bus_cap.l0sdly_ctrl;
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pcicfg.l1dly_ctrl = hal_com->bus_cap.l1dly_ctrl;
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|
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PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_,
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"%s : l0s/l1/l1ss/wake/crq/l0sdly/l1dly/clkdly = %#X/%#X/%#X/%#X/%#X/%#X/%#X/%#X \n",
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__func__, pcicfg.l0s_ctrl, pcicfg.l1_ctrl, pcicfg.l1ss_ctrl, pcicfg.wake_ctrl,
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pcicfg.crq_ctrl, pcicfg.l0sdly_ctrl, pcicfg.l1dly_ctrl, pcicfg.clkdly_ctrl);
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hsts = rtw_hal_mac_set_pcicfg(hal_info, &pcicfg);
|
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return hsts;
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}
|
|
enum rtw_hal_status hal_init_8852be(struct rtw_phl_com_t *phl_com,
|
struct hal_info_t *hal_info)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
struct rtw_hal_com_t *hal_com = hal_info->hal_com;
|
void *drv = phlcom_to_drvpriv(phl_com);
|
u32 len = 0;
|
u8 txch_num = 0;
|
|
txch_num = rtw_hal_query_txch_num(hal_info);
|
|
len = sizeof(struct rtw_wp_rpt_stats) * txch_num;
|
hal_com->trx_stat.wp_rpt_stats = _os_mem_alloc(drv, len);
|
if (hal_com->trx_stat.wp_rpt_stats == NULL) {
|
hal_status = RTW_HAL_STATUS_RESOURCE;
|
PHL_ERR("%s: alloc txch_map failed\n", __func__);
|
goto error_trx_stats_wp_rpt;
|
}
|
|
hal_info->txch_map = _os_mem_alloc(drv,
|
sizeof(struct mac_ax_txdma_ch_map));
|
if (hal_info->txch_map == NULL) {
|
hal_status = RTW_HAL_STATUS_RESOURCE;
|
PHL_ERR("%s: alloc txch_map failed\n", __func__);
|
goto error_txch_map;
|
}
|
|
hal_info->rpr_cfg = _os_mem_alloc(drv,
|
sizeof(struct mac_ax_host_rpr_cfg));
|
if (hal_info->rpr_cfg == NULL) {
|
hal_status = RTW_HAL_STATUS_RESOURCE;
|
PHL_ERR("%s: alloc rpr_cfg failed\n", __func__);
|
goto error_rpr_cfg;
|
}
|
|
hal_status = RTW_HAL_STATUS_SUCCESS;
|
|
return hal_status;
|
|
error_rpr_cfg:
|
_os_mem_free(drv,
|
hal_info->txch_map,
|
sizeof(struct mac_ax_txdma_ch_map));
|
error_txch_map:
|
_os_mem_free(drv,
|
hal_com->trx_stat.wp_rpt_stats,
|
sizeof(struct rtw_wp_rpt_stats) * txch_num);
|
error_trx_stats_wp_rpt:
|
return hal_status;
|
}
|
|
void hal_deinit_8852be(struct rtw_phl_com_t *phl_com,
|
struct hal_info_t *hal_info)
|
{
|
u8 txch_num = 0;
|
|
txch_num = rtw_hal_query_txch_num(hal_info);
|
|
_os_mem_free(phlcom_to_drvpriv(phl_com),
|
hal_info->hal_com->trx_stat.wp_rpt_stats,
|
sizeof(struct rtw_wp_rpt_stats) * txch_num);
|
_os_mem_free(phlcom_to_drvpriv(phl_com),
|
hal_info->txch_map,
|
sizeof(struct mac_ax_txdma_ch_map));
|
_os_mem_free(phlcom_to_drvpriv(phl_com),
|
hal_info->rpr_cfg,
|
sizeof(struct mac_ax_host_rpr_cfg));
|
}
|
|
enum rtw_hal_status hal_start_8852be(struct rtw_phl_com_t *phl_com,
|
struct hal_info_t *hal_info)
|
{
|
struct hal_init_info_t init_52be;
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
|
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
|
_hal_pre_init_8852be(phl_com, hal_info, &init_52be);
|
|
hal_status = hal_start_8852b(phl_com, hal_info, &init_52be);
|
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
|
|
PHL_ERR("hal_init_8852b: status = %u\n",hal_status);
|
return hal_status;
|
}
|
|
hal_status = hal_set_pcicfg_8852be(hal_info);
|
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
|
PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n",hal_status);
|
return hal_status;
|
}
|
|
hal_status = _hal_ltr_set_pcie_8852be(hal_info);
|
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
|
PHL_ERR("_hal_ltr_set_pcie_8852be: status = %u\n",hal_status);
|
return hal_status;
|
}
|
|
hal_status = _hal_ltr_sw_init_state_8852be(hal_info);
|
if(RTW_HAL_STATUS_SUCCESS != hal_status) {
|
PHL_ERR("_hal_ltr_sw_init_state_8852be: status = %u\n",hal_status);
|
return hal_status;
|
}
|
|
return hal_status;
|
}
|
|
enum rtw_hal_status hal_stop_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
|
if (TEST_STATUS_FLAG(phl_com->dev_state, RTW_DEV_SHUTTING_DOWN)) {
|
hal_status = _hal_aspm_disable_8852be(hal);
|
if (RTW_HAL_STATUS_SUCCESS != hal_status)
|
PHL_ERR("%s: _hal_aspm_disable_8852be status = %u\n",
|
__func__, hal_status);
|
}
|
|
hal_status = hal_stop_8852b(phl_com, hal);
|
return hal_status;
|
}
|
|
#ifdef CONFIG_WOWLAN
|
|
enum rtw_hal_status
|
hal_wow_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
|
struct rtw_phl_stainfo_t *sta)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
struct hal_init_info_t init_52be;
|
struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
|
|
FUNCIN_WSTS(hal_status);
|
|
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
|
if (true == phl_com->dev_cap.tx_mu_ru)
|
trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
|
else
|
trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
|
|
if (phl_com->dev_cap.quota_turbo == true)
|
trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
|
else
|
trx_info->qta_mode = MAC_AX_QTA_SCC;
|
/*
|
if (hal_info->hal_com->dbcc_en == false)
|
trx_info->qta_mode = MAC_AX_QTA_SCC;
|
else
|
trx_info->qta_mode = MAC_AX_QTA_DBCC;
|
*/
|
init_52be.ic_name = "rtl8852be";
|
|
hal_status = hal_wow_init_8852b(phl_com, hal_info, sta, &init_52be);
|
|
FUNCOUT_WSTS(hal_status);
|
return hal_status;
|
}
|
|
enum rtw_hal_status
|
hal_wow_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info,
|
struct rtw_phl_stainfo_t *sta)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
struct hal_init_info_t init_52be;
|
struct mac_ax_trx_info *trx_info = &init_52be.trx_info;
|
|
FUNCIN_WSTS(hal_status);
|
|
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
|
if (true == phl_com->dev_cap.tx_mu_ru)
|
trx_info->trx_mode = MAC_AX_TRX_SW_MODE;
|
else
|
trx_info->trx_mode = MAC_AX_TRX_HW_MODE;
|
|
if (phl_com->dev_cap.quota_turbo == true)
|
trx_info->qta_mode = MAC_AX_QTA_SCC_TURBO;
|
else
|
trx_info->qta_mode = MAC_AX_QTA_SCC;
|
/*
|
if (hal_info->hal_com->dbcc_en == false)
|
trx_info->qta_mode = MAC_AX_QTA_SCC;
|
else
|
trx_info->qta_mode = MAC_AX_QTA_DBCC;
|
*/
|
init_52be.ic_name = "rtl8852be";
|
|
hal_status = hal_wow_deinit_8852b(phl_com, hal_info, sta, &init_52be);
|
|
if (RTW_HAL_STATUS_SUCCESS != hal_status) {
|
|
PHL_ERR("hal_wow_deinit_8852be: status = %u\n", hal_status);
|
return hal_status;
|
}
|
|
if (RTW_HAL_STATUS_SUCCESS != hal_set_pcicfg_8852be(hal_info))
|
PHL_ERR("_hal_set_pcicfg_8852be: status = %u\n", hal_status);
|
|
|
FUNCOUT_WSTS(hal_status);
|
return hal_status;
|
}
|
|
#endif /* CONFIG_WOWLAN */
|
|
u32 hal_hci_cfg_8852be(struct rtw_phl_com_t *phl_com,
|
struct hal_info_t *hal, struct rtw_ic_info *ic_info)
|
{
|
struct hal_spec_t *hal_spec = phl_get_ic_spec(phl_com);
|
hal_spec->cts2_thres_en = true;
|
hal_spec->cts2_thres = 1792;
|
|
hal_spec->txbd_multi_tag = 8;
|
#ifdef RTW_WKARD_TXBD_UPD_LMT
|
hal_spec->txbd_upd_lmt = true;
|
#else
|
hal_spec->txbd_upd_lmt = false;
|
#endif
|
return RTW_HAL_STATUS_SUCCESS;
|
}
|
|
void hal_init_default_value_8852be(struct hal_info_t *hal)
|
{
|
init_default_value_8852b(hal);
|
|
hal_init_int_default_value_8852be(hal, INT_SET_OPT_HAL_INIT);
|
}
|
|
void hal_init_int_default_value_8852be(struct hal_info_t *hal, enum rtw_hal_int_set_opt opt)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_com->int_mask_default[0] = (u32)(
|
B_AX_RPQBD_FULL_INT_EN | /* RPQBD full */
|
B_AX_RDU_INT_EN | /* Rx Descriptor Unavailable */
|
#if 0
|
B_AX_RXDMA_STUCK_INT_EN | /* PCIE RX DMA Stuck */
|
B_AX_TXDMA_STUCK_INT_EN | /* PCIE TX DMA Stuck */
|
B_AX_PCIE_HOTRST_INT_EN | /* PCIE HOT Reset */
|
B_AX_PCIE_FLR_INT_EN | /* PCIE FLR */
|
B_AX_PCIE_PERST_INT_EN | /* PCIE PERST */
|
#endif
|
B_AX_RPQDMA_INT_EN | /* RPQ DMA OK */
|
B_AX_RXDMA_INT_EN | /* RXQ (Packet mode or Part2) DMA OK */
|
B_AX_HS0ISR_IND_INT_EN | /* FW C2H*/
|
B_AX_HD0ISR_IND_INT_EN | /* watchdog timer*/
|
#if 0
|
B_AX_TXDMA_CH12_INT_EN | /* FWCMDQ */
|
B_AX_TXDMA_CH9_INT_EN | /* */
|
B_AX_TXDMA_CH8_INT_EN | /* */
|
B_AX_TXDMA_ACH7_INT_EN | /* */
|
B_AX_TXDMA_ACH6_INT_EN | /* */
|
B_AX_TXDMA_ACH5_INT_EN | /* */
|
B_AX_TXDMA_ACH4_INT_EN | /* */
|
B_AX_TXDMA_ACH3_INT_EN | /* */
|
B_AX_TXDMA_ACH2_INT_EN | /* */
|
B_AX_TXDMA_ACH1_INT_EN | /* */
|
B_AX_TXDMA_ACH0_INT_EN | /* */
|
#endif
|
0);
|
|
hal_com->int_mask_default[1] = (u32)(
|
#if 0
|
B_AX_TXDMA_CH11_INT |
|
B_AX_TXDMA_CH10_INT |
|
#endif
|
0);
|
|
hal_com->intr.halt_c2h_int.val_default = (u32)(
|
B_AX_HALT_C2H_INT_EN |
|
0);
|
|
hal_com->intr.watchdog_timer_int.val_default = (u32)(
|
B_AX_WDT_PTFM_INT_EN |
|
0);
|
|
hal_com->int_mask[0] = hal_com->int_mask_default[0];
|
hal_com->int_mask[1] = hal_com->int_mask_default[1];
|
hal_com->intr.halt_c2h_int.val_mask = hal_com->intr.halt_c2h_int.val_default;
|
hal_com->intr.watchdog_timer_int.val_mask = hal_com->intr.watchdog_timer_int.val_default;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s : %08X, %08X, %08x, %08x\n", __func__,
|
hal_com->int_mask[0], hal_com->int_mask[1], hal_com->intr.halt_c2h_int.val_mask,
|
hal_com->intr.watchdog_timer_int.val_mask);
|
}
|
|
void hal_enable_int_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s ISR: %04X : %08X, %04X : %08X, %04X : %08X, %04X : %08X\n",
|
__func__,
|
R_AX_PCIE_HISR00, hal_read32(hal_com, R_AX_PCIE_HISR00),
|
R_AX_PCIE_HISR10, hal_read32(hal_com, R_AX_PCIE_HISR10),
|
R_AX_HISR0, hal_read32(hal_com, R_AX_HISR0),
|
R_AX_HD0ISR, hal_read32(hal_com, R_AX_HD0ISR)
|
);
|
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1]);
|
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask);
|
hal_write32(hal_com, R_AX_HD0IMR, hal_com->intr.watchdog_timer_int.val_mask);
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_INFO_, "%s IMR: %04X : %08X, %04X : %08X, %04X : %08X, %04X : %08X\n",
|
__func__,
|
R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
|
R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10),
|
R_AX_HIMR0, hal_read32(hal_com, R_AX_HIMR0),
|
R_AX_HD0IMR, hal_read32(hal_com, R_AX_HD0IMR)
|
);
|
|
}
|
|
void hal_disable_int_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
|
hal_write32(hal_com, R_AX_HIMR0, 0);
|
}
|
|
void hal_disable_int_isr_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
|
hal_write32(hal_com, R_AX_HIMR0, 0);
|
}
|
|
bool hal_recognize_int_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
bool recognized = false;
|
|
#ifndef CONFIG_SYNC_INTERRUPT
|
/* disable imr before cleaning isr */
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, 0);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, 0);
|
hal_write32(hal_com, R_AX_HIMR0, 0);
|
#endif /* CONFIG_SYNC_INTERRUPT */
|
|
/* save isr for sw usage, handling interrupt */
|
/* isr00 */
|
hal_com->int_array[0] = hal_read32(hal_com, R_AX_PCIE_HISR00);
|
hal_com->int_array[0] &= hal_com->int_mask[0];
|
|
/* isr10 */
|
hal_com->int_array[1] = hal_read32(hal_com, R_AX_PCIE_HISR10);
|
hal_com->int_array[1] &= hal_com->int_mask[1];
|
|
/* isr0 */
|
hal_com->intr.halt_c2h_int.intr = hal_read32(hal_com, R_AX_HISR0);
|
hal_com->intr.halt_c2h_int.intr &= hal_com->intr.halt_c2h_int.val_mask;
|
|
/* isr0 */
|
if (hal_com->int_array[0] & B_AX_HD0ISR_IND_INT_EN) {
|
hal_com->intr.watchdog_timer_int.intr = B_AX_WDT_PTFM_INT;
|
PHL_INFO("%s : R_AX_HD0ISR 0x%x.\n", __func__, hal_com->intr.watchdog_timer_int.intr);
|
hal_com->intr.watchdog_timer_int.intr &= hal_com->intr.watchdog_timer_int.val_mask;
|
/* clear int mask*/
|
hal_clear_int_mask_8852be(hal);
|
} else {
|
hal_com->intr.watchdog_timer_int.intr = 0;
|
}
|
|
if (hal_com->int_array[0] || hal_com->int_array[1] || hal_com->intr.halt_c2h_int.intr || hal_com->intr.watchdog_timer_int.intr)
|
recognized = true;
|
|
if (hal_com->intr.halt_c2h_int.intr)
|
PHL_WARN("%s : halt c2h interrupt is recognized (0x%x).\n", __func__, hal_com->intr.halt_c2h_int.intr);
|
|
if (hal_com->intr.watchdog_timer_int.intr)
|
PHL_WARN("%s : watchdog timer is recognized (0x%x).\n", __func__, hal_com->intr.watchdog_timer_int.intr);
|
|
#ifndef CONFIG_SYNC_INTERRUPT
|
/* clear isr */
|
hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
|
hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
|
hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
|
|
/* restore imr */
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
|
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
|
#endif /* CONFIG_SYNC_INTERRUPT */
|
return recognized;
|
}
|
|
void hal_clear_int_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_write32(hal_com, R_AX_PCIE_HISR00, hal_com->int_array[0]);
|
hal_write32(hal_com, R_AX_PCIE_HISR10, hal_com->int_array[1]);
|
hal_write32(hal_com, R_AX_HISR0, hal_com->intr.halt_c2h_int.intr);
|
}
|
|
void hal_clear_int_mask_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_com->int_mask[0] = 0;
|
hal_com->int_mask[1] = 0;
|
hal_com->intr.halt_c2h_int.val_mask = 0;
|
hal_com->intr.watchdog_timer_int.val_mask = 0;
|
}
|
|
void hal_restore_int_8852be(struct hal_info_t *hal)
|
{
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0] & 0xFFFFFFFF);
|
hal_write32(hal_com, R_AX_PCIE_HIMR10, hal_com->int_mask[1] & 0xFFFFFFFF);
|
hal_write32(hal_com, R_AX_HIMR0, hal_com->intr.halt_c2h_int.val_mask & 0xFFFFFFFF);
|
}
|
|
|
#define BIT_BCNDERR0_MSK BIT(16)
|
#define BIT_BCNDMAINT0_MSK BIT(20)
|
#define BIT_TXBCN0OK_MSK BIT(25)
|
#define BIT_TXBCN0ERR_MSK BIT(26)
|
|
static u32 hal_bcn_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
if (hal_com->int_array[0] & BIT_TXBCN0OK_MSK){
|
handled[0] |= BIT_TXBCN0OK_MSK;
|
ret = 1;
|
}
|
|
if (hal_com->int_array[0] & BIT_TXBCN0ERR_MSK){
|
handled[0] |= BIT_TXBCN0ERR_MSK;
|
ret = 1;
|
}
|
|
if (hal_com->int_array[0] & BIT_BCNDERR0_MSK){
|
handled[0] |= BIT_BCNDERR0_MSK;
|
ret = 1;
|
}
|
|
if (hal_com->int_array[0] & BIT_BCNDMAINT0_MSK){
|
handled[0] |= BIT_BCNDMAINT0_MSK;
|
ret = 1;
|
}
|
|
return ret;
|
}
|
|
static u32 hal_rx_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
static const u32 rx_handle_irq = (
|
B_AX_RXDMA_INT_EN |
|
B_AX_RDU_INT_EN |
|
B_AX_RPQDMA_INT_EN |
|
B_AX_RPQBD_FULL_INT_EN);
|
u32 handled0 = (hal_com->int_array[0] & rx_handle_irq);
|
|
if (handled0 == 0)
|
return ret;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ B4 : %08X (%08X)\n", handled0, hal_com->int_array[0]);
|
/* Disable RX interrupts, RX tasklet will enable them after processed RX */
|
hal_com->int_mask[0] &= ~rx_handle_irq;
|
#ifndef CONFIG_SYNC_INTERRUPT
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
|
#endif /* CONFIG_SYNC_INTERRUPT */
|
#ifdef PHL_RXSC_ISR
|
hal_com->rx_int_array = handled0;
|
#endif
|
handled[0] |= handled0;
|
ret = 1;
|
|
if (handled0 & B_AX_RDU_INT_EN)
|
hal_com->trx_stat.rx_rdu_cnt++;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ A4 : %08X (%08X)\n", handled0, hal_com->int_array[0]);
|
|
return ret;
|
|
}
|
|
static u32 hal_rp_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
static const u32 rp_handle_irq = (
|
B_AX_RXDMA_INT_EN |
|
B_AX_RDU_INT_EN |
|
B_AX_RPQDMA_INT_EN |
|
B_AX_RPQBD_FULL_INT_EN);
|
u32 handled0 = (hal_com->int_array[0] & rp_handle_irq);
|
|
if (handled0 == 0)
|
return ret;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ B4 : %08X (%08X)\n",
|
handled0, hal_com->int_array[0]);
|
/* Disable RX interrupts, RX tasklet will enable them after processed RX */
|
hal_com->int_mask[0] &= ~rp_handle_irq;
|
#ifndef CONFIG_SYNC_INTERRUPT
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
|
#endif /* CONFIG_SYNC_INTERRUPT */
|
#ifdef PHL_RXSC_ISR
|
hal_com->rx_int_array = handled0;
|
#endif
|
handled[0] |= handled0;
|
ret = 1;
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "RX IRQ A4 : %08X (%08X)\n",
|
handled0, hal_com->int_array[0]);
|
|
return ret;
|
|
}
|
|
static u32 hal_tx_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
u32 event0 = 0x0;
|
u32 event1 = 0x0;
|
|
event0 = hal_com->int_array[0] & (
|
B_AX_TXDMA_ACH0_INT |
|
B_AX_TXDMA_ACH1_INT |
|
B_AX_TXDMA_ACH2_INT |
|
B_AX_TXDMA_ACH3_INT |
|
B_AX_TXDMA_ACH4_INT |
|
B_AX_TXDMA_ACH5_INT |
|
B_AX_TXDMA_ACH6_INT |
|
B_AX_TXDMA_ACH7_INT |
|
B_AX_TXDMA_CH8_INT |
|
B_AX_TXDMA_CH9_INT |
|
B_AX_TXDMA_CH12_INT);
|
|
event1 = hal_com->int_array[1] & (
|
B_AX_TXDMA_CH10_INT |
|
B_AX_TXDMA_CH11_INT);
|
|
if(event0 != 0 || event1 != 0)
|
ret = 1;
|
|
handled[0] |= event0;
|
handled[1] |= event1;
|
|
return ret;
|
}
|
|
#define BIT_SETH2CDOK_MASK BIT(16)
|
static u32 hal_cmd_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
|
if (hal_com->int_array[3] & BIT_SETH2CDOK_MASK) {
|
handled[3] |= BIT_SETH2CDOK_MASK;
|
ret = 1;
|
}
|
|
return ret;
|
}
|
|
static u32 hal_halt_c2h_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
#if 1
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
if (hal_com->intr.halt_c2h_int.intr& B_AX_HALT_C2H_INT_EN) {
|
handled[0] |= B_AX_HALT_C2H_INT_EN;
|
ret = 1;
|
}
|
#endif
|
return ret;
|
}
|
|
static u32 hal_watchdog_timer_handler_8852be(struct hal_info_t *hal, u32 *handled)
|
{
|
u32 ret = 0;
|
#if 1
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
if (hal_com->intr.watchdog_timer_int.intr& B_AX_WDT_PTFM_INT_EN) {
|
handled[1] |= B_AX_WDT_PTFM_INT_EN;
|
ret = 1;
|
}
|
#endif
|
return ret;
|
}
|
|
u32 hal_int_hdler_8852be(struct hal_info_t *hal)
|
{
|
u32 int_hdler_msk = 0x0;
|
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
u32 handled[4] = {0};
|
u32 generalhandled[8] = {0};
|
|
/* <1> beacon related */
|
int_hdler_msk |= (hal_bcn_handler_8852be(hal, handled)<<0);
|
|
/* <2> Rx related */
|
int_hdler_msk |= (hal_rx_handler_8852be(hal, handled)<<1);
|
|
/* <3> Tx related */
|
int_hdler_msk |= (hal_tx_handler_8852be(hal, handled)<<2);
|
|
/* <4> Cmd related */
|
int_hdler_msk |= (hal_cmd_handler_8852be(hal, handled)<<3);
|
|
/*Start General interrupt type*/
|
/* <5> Halt C2H related */
|
int_hdler_msk |= (hal_halt_c2h_handler_8852be(hal, generalhandled)<<4);
|
|
/* <6> watchdog timer related */
|
int_hdler_msk |= (hal_watchdog_timer_handler_8852be(hal, generalhandled)<<5);
|
|
/* bit 7 : rsvd for gt3 interrupt*/
|
|
/* bit 8 : rx rp queue related */
|
int_hdler_msk |= (hal_rp_handler_8852be(hal, handled) << 8);
|
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : int_hdler_msk = 0x%x\n", __func__, int_hdler_msk);
|
|
if ((hal_com->int_array[0] & (~handled[0]))
|
|| (hal_com->int_array[1] & (~handled[1]))
|
|| (hal_com->int_array[2] & (~handled[2]))
|
|| (hal_com->int_array[3] & (~handled[3]))) {
|
/*if (printk_ratelimit()) */
|
{
|
PHL_WARN("Unhandled ISR => %x, %x, %x, %x, IMR : %08X, ISR : %08X\n",
|
(hal_com->int_array[0] & (~handled[0])),
|
(hal_com->int_array[1] & (~handled[1])),
|
(hal_com->int_array[2] & (~handled[2])),
|
(hal_com->int_array[3] & (~handled[3])),
|
hal_read32(hal_com, R_AX_PCIE_HIMR00),
|
hal_read32(hal_com, R_AX_PCIE_HISR00)
|
);
|
}
|
}
|
|
//General interrupt type not handled.
|
if ((hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])) ||
|
(hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1]))) {
|
/*if (printk_ratelimit()) */
|
{
|
PHL_WARN("Unhandled ISR => %x IMR : %08X, ISR : %08X; %x IMR : %08X, ISR : %08X\n",
|
(hal_com->intr.halt_c2h_int.intr & (~generalhandled[0])),
|
hal_read32(hal_com, R_AX_HIMR0),
|
hal_read32(hal_com, R_AX_HISR0),
|
(hal_com->intr.watchdog_timer_int.intr & (~generalhandled[1])),
|
hal_read32(hal_com, R_AX_HD0IMR),
|
hal_read32(hal_com, R_AX_HD0ISR));
|
}
|
}
|
|
|
return int_hdler_msk;
|
}
|
|
|
void hal_rx_int_restore_8852be(struct hal_info_t *hal)
|
{
|
|
struct rtw_hal_com_t *hal_com = hal->hal_com;
|
#ifndef CONFIG_SYNC_INTERRUPT
|
_os_spinlockfg sp_flags;
|
|
_os_spinlock(hal->phl_com->drv_priv, &hal->phl_com->imr_lock, _irq, &sp_flags);
|
#endif
|
|
hal_com->int_mask[0] |= (B_AX_RXDMA_INT_EN | B_AX_RPQDMA_INT_EN |
|
B_AX_RDU_INT_EN | B_AX_RPQBD_FULL_INT_EN);
|
#ifndef CONFIG_SYNC_INTERRUPT
|
hal_write32(hal_com, R_AX_PCIE_HIMR00, hal_com->int_mask[0]);
|
_os_spinunlock(hal->phl_com->drv_priv, &hal->phl_com->imr_lock, _irq, &sp_flags);
|
PHL_TRACE(COMP_PHL_DBG, _PHL_DEBUG_, "%s : %04X : %08X, %04X : %08X\n",
|
__func__,
|
R_AX_PCIE_HIMR00, hal_read32(hal_com, R_AX_PCIE_HIMR00),
|
R_AX_PCIE_HIMR10, hal_read32(hal_com, R_AX_PCIE_HIMR10)
|
);
|
#endif /* CONFIG_SYNC_INTERRUPT */
|
|
}
|
|
enum rtw_hal_status
|
hal_rx_rpq_int_check_8852be(u8 dma_ch, u32 hal_int_array)
|
{
|
enum rtw_hal_status hstatus = RTW_HAL_STATUS_FAILURE;
|
|
if (dma_ch == MAC_AX_RX_CH_RPQ && (hal_int_array & B_AX_RPQDMA_INT_EN))
|
hstatus = RTW_HAL_STATUS_SUCCESS;
|
|
return hstatus;
|
}
|
|
enum rtw_hal_status
|
hal_mp_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
struct hal_init_info_t init_52be;
|
|
FUNCIN_WSTS(hal_status);
|
|
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
|
|
init_52be.ic_name = "rtl8852be";
|
|
hal_status = hal_mp_init_8852b(phl_com, hal_info, &init_52be);
|
|
FUNCOUT_WSTS(hal_status);
|
return hal_status;
|
}
|
|
enum rtw_hal_status
|
hal_mp_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal_info)
|
{
|
enum rtw_hal_status hal_status = RTW_HAL_STATUS_FAILURE;
|
struct hal_init_info_t init_52be;
|
|
FUNCIN_WSTS(hal_status);
|
|
_os_mem_set(hal_to_drvpriv(hal_info), &init_52be, 0, sizeof(init_52be));
|
|
init_52be.ic_name = "rtl8852be";
|
|
hal_status = hal_mp_deinit_8852b(phl_com, hal_info, &init_52be);
|
|
if (RTW_HAL_STATUS_SUCCESS != hal_status) {
|
|
PHL_ERR("hal_mp_deinit_8852be: status = %u\n", hal_status);
|
return hal_status;
|
}
|
|
FUNCOUT_WSTS(hal_status);
|
return hal_status;
|
}
|
|
bool
|
hal_mp_path_chk_8852be(struct rtw_phl_com_t *phl_com, u8 ant_tx, u8 cur_phy)
|
{
|
if (phl_com->phy_cap[cur_phy].txss == 1 && ant_tx != RF_PATH_B)
|
return false;
|
else
|
return true;
|
}
|
