/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _RTL8852BE_HAL_H_
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#define _RTL8852BE_HAL_H_
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/* rtl8852BE_halinit.c */
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#define R_AX_HIMR0 0x01A0
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#define B_AX_HALT_C2H_INT_EN BIT(21)
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#define B_AX_RON_INT_EN BIT(20)
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#define B_AX_PDNINT_EN BIT(19)
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#define B_AX_SPSANA_OCP_INT_EN BIT(18)
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#define B_AX_SPS_OCP_INT_EN BIT(17)
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#define B_AX_BTON_STS_UPDATE_INT_EN BIT(16)
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#define B_AX_GPIOF_INT_EN BIT(15)
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#define B_AX_GPIOE_INT_EN BIT(14)
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#define B_AX_GPIOD_INT_EN BIT(13)
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#define B_AX_GPIOC_INT_EN BIT(12)
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#define B_AX_GPIOB_INT_EN BIT(11)
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#define B_AX_GPIOA_INT_EN BIT(10)
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#define B_AX_GPIO9_INT_EN BIT(9)
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#define B_AX_GPIO8_INT_EN BIT(8)
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#define B_AX_GPIO7_INT_EN BIT(7)
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#define B_AX_GPIO6_INT_EN BIT(6)
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#define B_AX_GPIO5_INT_EN BIT(5)
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#define B_AX_GPIO4_INT_EN BIT(4)
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#define B_AX_GPIO3_INT_EN BIT(3)
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#define B_AX_GPIO2_INT_EN BIT(2)
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#define B_AX_GPIO1_INT_EN BIT(1)
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#define B_AX_GPIO0_INT_EN BIT(0)
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#define R_AX_HISR0 0x01A4
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#define B_AX_HALT_C2H_INT BIT(21)
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#define B_AX_RON_INT BIT(20)
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#define B_AX_PDNINT BIT(19)
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#define B_AX_SPSANA_OCP_INT BIT(18)
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#define B_AX_SPS_OCP_INT BIT(17)
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#define B_AX_BTON_STS_UPDATE_INT BIT(16)
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#define B_AX_GPIOF_INT BIT(15)
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#define B_AX_GPIOE_INT BIT(14)
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#define B_AX_GPIOD_INT BIT(13)
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#define B_AX_GPIOC_INT BIT(12)
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#define B_AX_GPIOB_INT BIT(11)
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#define B_AX_GPIOA_INT BIT(10)
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#define B_AX_GPIO9_INT BIT(9)
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#define B_AX_GPIO8_INT BIT(8)
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#define B_AX_GPIO7_INT BIT(7)
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#define B_AX_GPIO6_INT BIT(6)
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#define B_AX_GPIO5_INT BIT(5)
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#define B_AX_GPIO4_INT BIT(4)
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#define B_AX_GPIO3_INT BIT(3)
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#define B_AX_GPIO2_INT BIT(2)
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#define B_AX_GPIO1_INT BIT(1)
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#define B_AX_GPIO0_INT BIT(0)
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#define R_AX_PCIE_HIMR00 0x10B0
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#define B_AX_HC00ISR_IND_INT_EN BIT(27)
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#define B_AX_HD1ISR_IND_INT_EN BIT(26)
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#define B_AX_HD0ISR_IND_INT_EN BIT(25)
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#define B_AX_HS0ISR_IND_INT_EN BIT(24)
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#define B_AX_RETRAIN_INT_EN BIT(21)
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#define B_AX_RPQBD_FULL_INT_EN BIT(20)
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#define B_AX_RDU_INT_EN BIT(19)
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#define B_AX_RXDMA_STUCK_INT_EN BIT(18)
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#define B_AX_TXDMA_STUCK_INT_EN BIT(17)
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#define B_AX_PCIE_HOTRST_INT_EN BIT(16)
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#define B_AX_PCIE_FLR_INT_EN BIT(15)
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#define B_AX_PCIE_PERST_INT_EN BIT(14)
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#define B_AX_TXDMA_CH12_INT_EN BIT(13)
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#define B_AX_TXDMA_CH9_INT_EN BIT(12)
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#define B_AX_TXDMA_CH8_INT_EN BIT(11)
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#define B_AX_TXDMA_ACH7_INT_EN BIT(10)
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#define B_AX_TXDMA_ACH6_INT_EN BIT(9)
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#define B_AX_TXDMA_ACH5_INT_EN BIT(8)
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#define B_AX_TXDMA_ACH4_INT_EN BIT(7)
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#define B_AX_TXDMA_ACH3_INT_EN BIT(6)
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#define B_AX_TXDMA_ACH2_INT_EN BIT(5)
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#define B_AX_TXDMA_ACH1_INT_EN BIT(4)
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#define B_AX_TXDMA_ACH0_INT_EN BIT(3)
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#define B_AX_RPQDMA_INT_EN BIT(2)
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#define B_AX_RXP1DMA_INT_EN BIT(1)
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#define B_AX_RXDMA_INT_EN BIT(0)
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#define R_AX_PCIE_HISR00 0x10B4
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#define B_AX_HC00ISR_IND_INT BIT(27)
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#define B_AX_HD1ISR_IND_INT BIT(26)
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#define B_AX_HD0ISR_IND_INT BIT(25)
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#define B_AX_HS0ISR_IND_INT BIT(24)
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#define B_AX_RETRAIN_INT BIT(21)
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#define B_AX_RPQBD_FULL_INT BIT(20)
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#define B_AX_RDU_INT BIT(19)
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#define B_AX_RXDMA_STUCK_INT BIT(18)
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#define B_AX_TXDMA_STUCK_INT BIT(17)
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#define B_AX_PCIE_HOTRST_INT BIT(16)
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#define B_AX_PCIE_FLR_INT BIT(15)
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#define B_AX_PCIE_PERST_INT BIT(14)
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#define B_AX_TXDMA_CH12_INT BIT(13)
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#define B_AX_TXDMA_CH9_INT BIT(12)
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#define B_AX_TXDMA_CH8_INT BIT(11)
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#define B_AX_TXDMA_ACH7_INT BIT(10)
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#define B_AX_TXDMA_ACH6_INT BIT(9)
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#define B_AX_TXDMA_ACH5_INT BIT(8)
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#define B_AX_TXDMA_ACH4_INT BIT(7)
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#define B_AX_TXDMA_ACH3_INT BIT(6)
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#define B_AX_TXDMA_ACH2_INT BIT(5)
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#define B_AX_TXDMA_ACH1_INT BIT(4)
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#define B_AX_TXDMA_ACH0_INT BIT(3)
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#define B_AX_RPQDMA_INT BIT(2)
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#define B_AX_RXP1DMA_INT BIT(1)
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#define B_AX_RXDMA_INT BIT(0)
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#define R_AX_PCIE_HIMR10 0x13B0
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#define B_AX_HC10ISR_IND_INT_EN BIT(28)
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#define B_AX_TXDMA_CH11_INT_EN BIT(12)
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#define B_AX_TXDMA_CH10_INT_EN BIT(11)
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#define R_AX_PCIE_HISR10 0x13B4
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#define B_AX_HC10ISR_IND_INT BIT(28)
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#define B_AX_TXDMA_CH11_INT BIT(12)
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#define B_AX_TXDMA_CH10_INT BIT(11)
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enum rtw_hal_status hal_get_efuse_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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#ifdef CONFIG_PCI_HCI
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enum rtw_hal_status hal_set_pcicfg_8852be(struct hal_info_t *hal_info);
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#endif /* CONFIG_PCI_HCI */
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enum rtw_hal_status hal_init_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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void hal_deinit_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status hal_start_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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enum rtw_hal_status hal_stop_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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#ifdef CONFIG_WOWLAN
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enum rtw_hal_status hal_wow_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
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enum rtw_hal_status hal_wow_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal, struct rtw_phl_stainfo_t *sta);
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#endif /* CONFIG_WOWLAN */
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enum rtw_hal_status hal_mp_init_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal);
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enum rtw_hal_status hal_mp_deinit_8852be(struct rtw_phl_com_t *phl_com, struct hal_info_t *hal);
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bool hal_mp_path_chk_8852be(struct rtw_phl_com_t *phl_com, u8 ant_tx, u8 cur_phy);
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void hal_init_default_value_8852be(struct hal_info_t *hal);
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void hal_init_int_default_value_8852be(struct hal_info_t *hal, enum rtw_hal_int_set_opt opt);
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u32 hal_hci_cfg_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal,
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struct rtw_ic_info *ic_info);
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void init_hal_spec_8852be(struct rtw_phl_com_t *phl_com,
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struct hal_info_t *hal);
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void hal_disable_int_isr_8852be(struct hal_info_t *hal);
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void hal_enable_int_8852be(struct hal_info_t *hal);
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void hal_disable_int_8852be(struct hal_info_t *hal);
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bool hal_recognize_int_8852be(struct hal_info_t *hal);
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void hal_clear_int_8852be(struct hal_info_t *hal);
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void hal_clear_int_mask_8852be(struct hal_info_t *hal);
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void hal_restore_int_8852be(struct hal_info_t *hal);
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u32 hal_int_hdler_8852be(struct hal_info_t *hal);
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void hal_rx_int_restore_8852be(struct hal_info_t *hal);
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enum rtw_hal_status
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hal_get_pcicfg_8852be(struct hal_info_t *hal_info,
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struct rtw_pcie_cfgspc_param *cfg);
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#ifdef PHL_RXSC_ISR
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enum rtw_hal_status
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hal_rx_rpq_int_check_8852be(u8 dma_ch, u32 hal_int_array);
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#endif
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/* rtl8852BE_ops.c */
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#endif /* _RTL8852BE_HAL_H_ */
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