/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALRF_IQK_H_
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#define _HALRF_IQK_H_
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/*@--------------------------Define Parameters-------------------------------*/
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#define TXIQK 0
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#define RXIQK 1
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#define RXIQK1 2
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#define RXIQK2 3
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#define NBTXK 4
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#define NBRXK 5
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//#define NUM 2
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#define ID_TXAGC 0x0
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#define ID_FLoK_coarse 0x1
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#define ID_FLoK_fine 0x2
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#define ID_TXK 0x3
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#define ID_RXAGC 0x4
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#define ID_RXK 0x5
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#define ID_NBTXK 0x6
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#define ID_NBRXK 0x7
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#define ID_FLOK_vbuffer 0x8
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#define ID_A_FLoK_coarse 0x9
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#define ID_G_FLoK_coarse 0xa
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#define ID_A_FLoK_fine 0xb
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#define ID_G_FLoK_fine 0xc
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#define ID_TX_PAD_GainGapK 0xe
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#define ID_TX_PA_GainGapK 0xf
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#define ID_IQK_Restore 0x10
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/*@-----------------------End Define Parameters-----------------------*/
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struct halrf_iqk_info {
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bool lok_cor_fail[2][NUM]; /*channel/path */
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bool lok_fin_fail[2][NUM]; /*channel/path */
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bool iqk_tx_fail[2][NUM]; /*channel/path */
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bool iqk_rx_fail[2][NUM]; /*channel/path */
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u32 iqk_cnt;
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u32 iqk_fail_cnt;
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bool segment_iqk;
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bool is_iqk_enable;
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bool is_iqk_init;
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bool is_reload;
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u32 iqk_channel[2];
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u8 iqk_band[NUM];
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u8 iqk_ch[NUM];
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u8 iqk_bw[NUM];
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u8 kcount;
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u8 iqk_times;
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u8 rxiqk_step;
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u8 iqk_step;
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u8 version;
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u32 lok_idac[2][NUM];
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u32 lok_vbuf[2][NUM];
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u32 iqc_gain;
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u32 rftxgain[NUM];
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u32 rfrxgain[NUM];
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u32 nb_txcfir[NUM];
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u32 nb_rxcfir[NUM];
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u32 rximr[NUM];
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u32 syn1to2;
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u32 bp_txkresult[2];
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u32 bp_rxkresult[2];
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u32 bp_lokresult[2];
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u32 bp_iqkenable[2];
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u32 reload_cnt;
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bool is_wb_txiqk[2];
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bool is_wb_rxiqk[2];
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bool is_nbiqk;
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bool iqk_fft_en;
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bool iqk_xym_en;
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bool iqk_sram_en;
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bool iqk_cfir_en;
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u8 ther_avg[2][8]; /*path*/
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u8 ther_avg_idx;
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u8 thermal[2];
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bool thermal_rek_en;
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u8 iqk_mcc_ch[2][NUM];
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u8 iqk_table_idx[NUM];
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bool is_fw_iqk;
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u32 time;
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u32 lok_0x58[2];
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u32 lok_0x5c[2];
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u32 lok_0x7c[2];
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};
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enum halrf_iqk_dz{
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DZ_IQK_ALIMTK_TIMEOUT1 = BIT(0),
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DZ_IQK_ALIMTK_TIMEOUT2 = BIT(1),
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DZ_LOK_ALIMTK = BIT(2),
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DZ_TXIQK_ALIMTK = BIT(3),
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DZ_RXIQK_ALIMTK = BIT(4),
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DZ_TXXYM_ALIMTK = BIT(5),
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DZ_RXXYM_ALIMTK = BIT(6),
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DZ_RXAGC_ALIMTK = BIT(7),
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};
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void halrf_iqk_init(struct rf_info *rf);
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void halrf_iqk(struct rf_info *rf, enum phl_phy_idx phy_idx, bool force);
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u32 halrf_get_iqk_ver(struct rf_info *rf);
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void halrf_iqk_toneleakage(void *rf_void, u8 path);
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void halrf_nbiqk_enable(void *rf_void, bool iqk_nbiqk_en);
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void halrf_iqk_tx_bypass(void *rf_void, u8 path);
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void halrf_iqk_rx_bypass(void *rf_void, u8 path);
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void halrf_iqk_lok_bypass(void *rf_void, u8 path);
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void halrf_iqk_xym_enable(void *rf_void, bool iqk_xym_en);
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void halrf_iqk_fft_enable(void *rf_void, bool iqk_fft_en);
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void halrf_iqk_cfir_enable(void *rf_void, bool iqk_cfir_en);
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void halrf_iqk_sram_enable(void *rf_void, bool iqk_sram_en);
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void halrf_iqk_reload(void *rf_void, u8 path);
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void halrf_iqk_dbcc(void *rf_void, u8 path);
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u8 halrf_iqk_get_mcc_ch0(void *rf_void);
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u8 halrf_iqk_get_mcc_ch1(void *rf_void);
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void halrf_enable_fw_iqk(void *rf_void, bool is_fw_iqk);
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u8 halrf_iqk_get_rxevm(void *rf_void);
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u32 halrf_iqk_get_rximr(void *rf_void, u8 path, u32 idx);
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bool halrf_check_fwiqk_done(struct rf_info *rf);
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#endif
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