/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALRF_INTERFACE_H__
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#define __HALRF_INTERFACE_H__
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//#ifdef CONFIG_FW_IO_OFLD_SUPPORT
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#ifdef CONFIG_PHL_IO_OFLD
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#define HALRF_CONFIG_FW_IO_OFLD_SUPPORT
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#endif
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#ifdef CONFIG_FW_DBCC_OFLD_SUPPORT
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#define HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT
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#endif
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#ifdef CONFIG_HAL_THERMAL_PROTECT
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#define HALRF_THERMAL_PROTECT_SUPPORT
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#endif
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#define CF_PHL_BB_CTRL_RX_CCA
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/*@--------------------------[Define] ---------------------------------------*/
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/*[IO Reg]*/
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#define RF_OFST 0x10000
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#define halrf_btc_ntfy(rf, idx, type, process) rtw_hal_btc_wl_rfk_ntfy((rf)->hal_com, idx, type, process)
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#define halrf_r32(rf, addr) hal_read32((rf)->hal_com, (addr | RF_OFST))
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#define halrf_r16(rf, addr) hal_read16((rf)->hal_com, (addr | RF_OFST))
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#define halrf_r8(rf, addr) hal_read8((rf)->hal_com, (addr | RF_OFST))
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#define halrf_w32(rf, addr, val) hal_write32((rf)->hal_com, (addr | RF_OFST), val)
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#define halrf_w16(rf, addr, val) hal_write16((rf)->hal_com, (addr | RF_OFST), val)
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#define halrf_w8(rf, addr, val) hal_write8((rf)->hal_com, (addr | RF_OFST), val)
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//#define halrf_rrf(rf, path, addr, mask) rtw_hal_read_rf_reg((rf)->hal_com, path, addr, mask)
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/*#define halrf_wrf(rf, path, addr, mask, val) rtw_hal_write_rf_reg((rf)->hal_com, path, addr, mask, val)*/
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/*#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val)*/
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//#define halrf_rmac32(rf, addr) hal_read32((rf)->hal_com, addr)
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#define halrf_wmac32(rf, addr, val) hal_write32((rf)->hal_com, addr, val)
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#define halrf_read_mem(rf, addr, cnt, pmem) hal_read_mem((rf)->hal_com, addr, cnt, pmem)
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/*[TX]*/
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#define halrf_tx_pause(rf, band_idx, tx_pause, rson) rtw_hal_tx_pause((rf)->hal_com, band_idx, tx_pause, rson)
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#define halrf_tx_mode_switch(rf, phy_idx, mode) rtw_hal_bb_tx_mode_switch((rf)->hal_com, phy_idx, mode)
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#define halrf_query_regulation_info(rf, info) rtw_hal_query_regulation((rf)->phl_com->phl_priv, info)
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#define halrf_hal_bb_backup_info(rf, phy_idx) rtw_hal_bb_backup_info((rf)->hal_com, phy_idx)
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#define halrf_hal_bb_restore_info(rf, phy_idx) rtw_hal_bb_restore_info((rf)->hal_com, phy_idx)
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/*[Delay]*/
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#define halrf_delay_ms(rf, ms) _os_delay_ms(rf->hal_com->drv_priv, ms)
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#define halrf_os_delay_us(rf, us) _os_delay_us(rf->hal_com->drv_priv, us)
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/*[Memory Access]*/
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#define halrf_mem_set(rf, buf, value, size) _os_mem_set(rf->hal_com->drv_priv, (void *)buf, value, size)
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#define halrf_mem_cpy(rf, dest, src, size) _os_mem_cpy(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
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#define halrf_mem_cmp(rf, dest, src, size) _os_mem_cmp(rf->hal_com->drv_priv, (void *)dest, (void *)src, size)
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#define halrf_mem_alloc(rf, buf_sz) hal_mem_alloc(rf->hal_com, buf_sz)
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#define halrf_mem_free(rf, buf, buf_sz) hal_mem_free(rf->hal_com, (void *)buf, buf_sz)
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/*[Timer]*/
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#define halrf_init_timer(rf, timer, call_back_func, context, sz_id) _os_init_timer(rf->hal_com->drv_priv, timer, call_back_func, context, sz_id)
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#define halrf_set_timer(rf, timer, ms_delay) _os_set_timer(rf->hal_com->drv_priv, timer, ms_delay)
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#define halrf_cancel_timer(rf, timer) _os_cancel_timer(rf->hal_com->drv_priv, timer)
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#define halrf_release_timer(rf, timer) _os_release_timer(rf->hal_com->drv_priv, timer)
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/*efuse*/
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#ifndef RTW_FLASH_98D
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#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_efuse_get_info((rf)->hal_com, info_type, (void *)value, size)
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#else
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#define halrf_efuse_get_info(rf, info_type, value, size) rtw_hal_flash_get_info((rf)->hal_com, info_type, (void *)value, size)
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#endif /*RTW_FLASH_98D*/
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#define halrf_phy_efuse_get_info(rf, addr, size, value) rtw_hal_mac_read_phy_efuse((rf)->hal_com, addr, size, value)
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/*GPIO*/
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/*#ifndef RF_8852B_SUPPORT*/
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#define halrf_gpio_setting_all(rf, rfe_idx) rtw_hal_bb_gpio_setting_all((rf)->hal_com, rfe_idx)
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#define halrf_gpio_setting(rf, gpio_idx, path, inv, src) rtw_hal_bb_gpio_setting((rf)->hal_com, gpio_idx, path, inv, src)
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#define halrf_set_gpio_func(rf, func, gpio_cfg) rtw_hal_mac_set_gpio_func((rf)->hal_com, func, gpio_cfg)
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/*#endif*/
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/*Set power by rate, power limit, power */
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#define halrf_mac_write_pwr_limit_rua_reg(rf, band) rtw_hal_mac_write_pwr_limit_rua_reg((rf)->hal_com, band)
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#define halrf_mac_write_pwr_limit_reg(rf, band) rtw_hal_mac_write_pwr_limit_reg((rf)->hal_com, band)
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#define halrf_mac_write_pwr_by_rate_reg(rf, band) rtw_hal_mac_write_pwr_by_rate_reg((rf)->hal_com, band)
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#define halrf_bb_set_tx_pow_ref(rf, phy_idx) rtw_hal_bb_set_tx_pow_ref((rf)->hal_com, phy_idx)
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#define halrf_mac_write_pwr_ofst_mode(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_mode((rf)->hal_com, phy_idx)
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#define halrf_mac_write_pwr_ofst_bw(rf, phy_idx) rtw_hal_mac_write_pwr_ofst_bw((rf)->hal_com, phy_idx)
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#define halrf_mac_write_pwr_limit_en(rf, phy_idx) rtw_hal_mac_write_pwr_limit_en((rf)->hal_com, phy_idx)
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#define halrf_bb_set_pow_patten_sharp(rf, channel, is_cck, sharp_id, phy_idx) rtw_hal_bb_set_pow_patten_sharp((rf)->hal_com, channel, is_cck, sharp_id, phy_idx)
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#if defined(HALRF_CONFIG_FW_DBCC_OFLD_SUPPORT) || defined(HALRF_CONFIG_FW_IO_OFLD_SUPPORT)
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/*FW offload*/
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#define halrf_mac_add_cmd_ofld(rf, cmd) rtw_hal_mac_add_cmd_ofld((rf)->hal_com, cmd)
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#endif
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/*BB related*/
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#define halrf_bb_ctrl_rx_cca(rf, cca_en, phy_idx) rtw_hal_bb_ctrl_rx_cca((rf)->hal_com, cca_en, phy_idx)
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#define halrf_bb_ctrl_cck_en(rf, cck_en, phy_idx) rtw_hal_bb_ctrl_cck_en((rf)->hal_com, cck_en, phy_idx)
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#define halrf_bb_query_cck_en(rf, phy_idx) rtw_hal_bb_query_cck_en((rf)->hal_com, phy_idx)
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#define halrf_bb_adc_cfg(rf, bw, path, phy_idx) rtw_hal_bb_adc_cfg((rf)->hal_com, bw, path, phy_idx)
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#define halrf_mutex_init(rf, mutex) hal_mutex_init((rf)->hal_com, mutex)
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#define halrf_mutex_deinit(rf, mutex) hal_mutex_deinit((rf)->hal_com, mutex)
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#define halrf_mutex_lock(rf, mutex) hal_mutex_lock((rf)->hal_com, mutex)
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#define halrf_mutex_unlock(rf, mutex) hal_mutex_unlock((rf)->hal_com, mutex)
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/*SER control*/
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#define halrf_mac_ctrl_ser(rf, rsn, en) rtw_hal_mac_ctrl_ser((rf)->hal_com, rsn, en)
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#ifdef CONFIG_PHL_DFS
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/*BB DFS*/
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#define halrf_is_radar_detect_enabled(rf, phy_idx) rtw_hal_is_radar_detect_enabled((rf)->hal_com, phy_idx)
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#define halrf_bb_dfs_rpt_cfg(rf, phy_idx, dfs_en) rtw_hal_bb_dfs_rpt_cfg((rf)->hal_com, phy_idx, dfs_en)
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#endif
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/*@--------------------------[Enum]------------------------------------------*/
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/*@--------------------------[Structure]-------------------------------------*/
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/*@--------------------------[Prptotype]-------------------------------------*/
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struct bb_info;
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u32 halrf_cal_bit_shift(u32 bit_mask);
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u32 halrf_get_sys_time(struct rf_info *rf);
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void halrf_wmac(struct rf_info *rf, u32 addr, u32 mask, u32 val);
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void halrf_wreg(struct rf_info *rf, u32 addr, u32 bit_mask, u32 val);
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bool halrf_polling_bb(struct rf_info *rf, u32 addr, u32 mask, u32 val, u32 count);
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bool halrf_polling_rf(struct rf_info *rf, u32 path, u32 addr, u32 mask, u32 val, u32 count);
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u32 halrf_rreg(struct rf_info *rf, u32 addr, u32 bit_mask);
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void halrf_wrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask, u32 val);
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u32 halrf_rrf(struct rf_info *rf, enum rf_path path, u32 addr, u32 mask);
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void halrf_fill_h2c_cmd(struct rf_info *rf, u16 cmdlen, u8 cmdid,
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u8 classid, u32 cmdtype, u32 *pval);
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void halrf_delay_us(struct rf_info *rf, u32 count);
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u32 halrf_rmac32(struct rf_info *rf, u32 addr);
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#endif
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