/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#include "../halrf_precomp.h"
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#ifdef RF_8852B_SUPPORT
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u8 halrf_get_thermal_8852b(struct rf_info *rf, enum rf_path rf_path)
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{
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halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
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halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x0);
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halrf_wrf(rf, rf_path, 0x42, BIT(19), 0x1);
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halrf_delay_us(rf, 200);
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return (u8)halrf_rrf(rf, rf_path, 0x42, 0x0007e);
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}
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u32 halrf_mac_get_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
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u32 addr, u32 mask)
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{
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struct rtw_hal_com_t *hal = rf->hal_com;
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u32 result, ori_val, bit_shift, reg_val;
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result = rtw_hal_mac_get_pwr_reg(hal, phy, addr, &ori_val);
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if (result)
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RF_WARNING("=======>%s Get MAC(0x%x) fail, error code=%d\n",
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__func__, addr, result);
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else
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RF_DBG(rf, DBG_RF_POWER, "Get MAC(0x%x) ok!!! 0x%08x\n",
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addr, ori_val);
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bit_shift = halrf_cal_bit_shift(mask);
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reg_val = (ori_val & mask) >> bit_shift;
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return reg_val;
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}
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u32 halrf_mac_set_pwr_reg_8852b(struct rf_info *rf, enum phl_phy_idx phy,
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u32 addr, u32 mask, u32 val)
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{
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struct rtw_hal_com_t *hal = rf->hal_com;
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u32 result;
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result = rtw_hal_mac_write_msk_pwr_reg(hal, phy, addr, mask, val);
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if (result) {
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RF_WARNING("=======>%s Set MAC(0x%x[0x%08x]) fail, error code=%d\n",
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__func__, addr, mask, result);
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return false;
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} else
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RF_DBG(rf, DBG_RF_POWER, "Set MAC(0x%x[0x%08x])=0x%08x ok!!! \n",
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addr, mask, val);
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return result;
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}
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void halrf_wlan_tx_power_control_8852b(struct rf_info *rf,
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enum phl_phy_idx phy, enum phl_pwr_ctrl pwr_ctrl_idx,
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u32 tx_power_val, bool enable)
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{
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u32 phy_tmp;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] ==>%s phy=%d pwr_ctrl_idx=%d tx_power_val=%d enable=%d\n",
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__func__, phy, pwr_ctrl_idx, tx_power_val, enable);
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if (rf->hal_com->dbcc_en)
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phy_tmp = phy;
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else
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phy_tmp = HW_PHY_0;
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if (enable == false) {
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if (pwr_ctrl_idx == ALL_TIME_CTRL) {
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/*all-time control Disable*/
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd200, 0x3ff, 0x0);
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} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
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/*GNT_BT control Disable*/
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, BIT(1), 0x0);
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, 0xff8, 0x0);
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}
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} else {
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if (pwr_ctrl_idx == ALL_TIME_CTRL) {
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd200, 0x3ff,
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((tx_power_val & 0x1ff) | BIT(9)));
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} else if (pwr_ctrl_idx == GNT_TIME_CTRL) {
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, BIT(1), 0x1);
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halrf_mac_set_pwr_reg_8852b(rf, phy_tmp, 0xd220, 0xff8, tx_power_val & 0x1ff);
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} else {
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RF_WARNING("[Pwr Ctrl] ==>%s (pwr_ctrl_idx = %d) don't exist !!!\n",
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__func__, pwr_ctrl_idx);
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}
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}
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}
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bool halrf_wl_tx_power_control_8852b(struct rf_info *rf, u32 tx_power_val)
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{
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struct halrf_pwr_info *pwr = &rf->pwr_info;
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u32 result;
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s32 tmp_pwr;
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u8 phy = 0;
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u32 all_time_control = 0;
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u32 gnt_bt_control = 0;
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RF_DBG(rf, DBG_RF_POWER, "=======>%s\n", __func__);
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all_time_control = tx_power_val & 0xffff;
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gnt_bt_control = (tx_power_val & 0xffff0000) >> 16;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl]tx_power_val=0x%x all_time_control=0x%x gnt_bt_control=0x%x\n",
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tx_power_val, all_time_control, gnt_bt_control);
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if (all_time_control == 0xffff) {
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/*Coex Disable*/
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pwr->coex_pwr_ctl_enable = false;
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pwr->coex_pwr = 0;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Disable all_time_control=0xffff!!!\n");
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} else if (all_time_control == 0xeeee) {
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/*DPK Disable*/
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pwr->dpk_pwr_ctl_enable = false;
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pwr->dpk_pwr = 0;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Disable all_time_control=0xeeee\n");
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} else {
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if (all_time_control & BIT(15)) {
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/*DPK*/
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pwr->dpk_pwr_ctl_enable = true;
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pwr->dpk_pwr = all_time_control & 0x1ff;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] DPK Enable Set pwr->dpk_pwr = %d\n",
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pwr->dpk_pwr);
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} else {
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/*Coex*/
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pwr->coex_pwr_ctl_enable = true;
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pwr->coex_pwr = all_time_control & 0x1ff;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] Coex Enable Set pwr->coex_pwr = %d\n",
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pwr->coex_pwr);
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}
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}
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if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == false) {
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tmp_pwr = pwr->coex_pwr;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=false tmp_pwr=%d\n",
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tmp_pwr);
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} else if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == true) {
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tmp_pwr = pwr->dpk_pwr;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=false dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
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tmp_pwr);
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} else if (pwr->coex_pwr_ctl_enable == true && pwr->dpk_pwr_ctl_enable == true) {
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if (pwr->coex_pwr > pwr->dpk_pwr)
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tmp_pwr = pwr->dpk_pwr;
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else
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tmp_pwr = pwr->coex_pwr;
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RF_DBG(rf, DBG_RF_POWER, "[Pwr Ctrl] coex_pwr_ctl_enable=true dpk_pwr_ctl_enable=true tmp_pwr=%d\n",
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tmp_pwr);
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} else
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tmp_pwr = 0;
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if (pwr->coex_pwr_ctl_enable == false && pwr->dpk_pwr_ctl_enable == false) {
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/*all-time control Disable*/
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0x3ff, 0x0);
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if (result) {
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RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
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__func__, result);
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return false;
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} else {
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RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
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rf->is_coex = false;
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}
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} else {
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/*all-time control*/
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd200, 0x3ff, ((tmp_pwr & 0x1ff) | BIT(9)));
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if (result) {
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RF_WARNING("=======>%s Set MAC(0xd200) fail, error code=%d\n",
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__func__, result);
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return false;
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} else {
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RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd200) ok!!!\n");
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rf->is_coex = true;
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}
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}
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if (gnt_bt_control == 0xffff) {
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/*GNT_BT control*/
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RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n",
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__func__, gnt_bt_control);
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x0);
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xff8, 0x0);
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if (result) {
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RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
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__func__, result);
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return false;
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} else {
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RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
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rf->is_coex = false;
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}
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} else {
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/*GNT_BT control*/
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RF_DBG(rf, DBG_RF_POWER, "=======>%s gnt_bt_control = 0x%x\n",
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__func__, gnt_bt_control);
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, BIT(1), 0x1);
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result = halrf_mac_set_pwr_reg_8852b(rf, phy, 0xd220, 0xff8, gnt_bt_control & 0x1ff);
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if (result) {
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RF_WARNING("=======>%s Set MAC(0xd220) fail, error code=%d\n",
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__func__, result);
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return false;
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} else {
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RF_DBG(rf, DBG_RF_POWER, "Set MAC(0xd220) ok!!!\n");
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rf->is_coex = true;
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}
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}
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return true;
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}
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s8 halrf_get_ther_protected_threshold_8852b(struct rf_info *rf)
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{
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u8 tmp_a, tmp_b, tmp;
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u8 therml_max = 0x32;
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tmp_a = halrf_get_thermal(rf, RF_PATH_A);
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tmp_b = halrf_get_thermal(rf, RF_PATH_B);
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#ifdef HALRF_THERMAL_PROTECT_SUPPORT
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if (rf->phl_com->dev_sw_cap.thermal_threshold != 0xff)
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therml_max = rf->phl_com->dev_sw_cap.thermal_threshold;
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#endif
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if (tmp_a > tmp_b)
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tmp = tmp_a;
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else
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tmp = tmp_b;
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if (tmp > therml_max)
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return -1; /*Tx duty reduce*/
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else if (tmp < therml_max - 2)
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return 1; /*Tx duty up*/
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else
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return 0; /*Tx duty the same*/
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}
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s8 halrf_xtal_tracking_offset_8852b(struct rf_info *rf,
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enum phl_phy_idx phy)
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{
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struct halrf_xtal_info *xtal_trk = &rf->xtal_track;
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u8 thermal_a = 0xff, thermal_b = 0xff;
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u8 tmp_a, tmp_b, tmp;
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s8 xtal_ofst = 0;
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RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s phy=%d\n",
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__func__, phy);
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tmp_a = halrf_get_thermal(rf, RF_PATH_A);
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tmp_b = halrf_get_thermal(rf, RF_PATH_B);
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halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_A, &thermal_a, 1);
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halrf_efuse_get_info(rf, EFUSE_INFO_RF_THERMAL_B, &thermal_b, 1);
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if (thermal_a == 0xff || thermal_b == 0xff ||
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thermal_a == 0x0 || thermal_b == 0x0) {
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RF_DBG(rf, DBG_RF_XTAL_TRACK, "======>%s PG ThermalA=%d ThermalB=%d\n",
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__func__, thermal_a, thermal_b);
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return 0;
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}
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if (tmp_a > tmp_b) {
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if (tmp_a > thermal_a) {
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tmp = tmp_a - thermal_a;
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if (tmp >= DELTA_SWINGIDX_SIZE)
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tmp = DELTA_SWINGIDX_SIZE - 1;
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xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
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} else {
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tmp = thermal_a - tmp_a;
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if (tmp >= DELTA_SWINGIDX_SIZE)
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tmp = DELTA_SWINGIDX_SIZE - 1;
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xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
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}
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} else {
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if (tmp_b > thermal_b) {
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tmp = tmp_b - thermal_b;
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if (tmp >= DELTA_SWINGIDX_SIZE)
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tmp = DELTA_SWINGIDX_SIZE - 1;
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xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_p[tmp];
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} else {
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tmp = thermal_b - tmp_b;
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if (tmp >= DELTA_SWINGIDX_SIZE)
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tmp = DELTA_SWINGIDX_SIZE - 1;
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xtal_ofst = xtal_trk->delta_swing_xtal_table_idx_n[tmp];
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}
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}
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RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalA=%d ThermalA=%d\n",
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thermal_a, tmp_a);
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RF_DBG(rf, DBG_RF_XTAL_TRACK, "PG ThermalB=%d ThermalB=%d\n",
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thermal_b, tmp_b);
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RF_DBG(rf, DBG_RF_XTAL_TRACK, "xtal_ofst[%d]=%d\n",
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tmp, xtal_ofst);
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return xtal_ofst;
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}
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void halrf_rfe_ant_num_chk_8852b(struct rf_info *rf)
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{
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struct phy_hw_cap_t *phy_hw = rf->hal_com->phy_hw_cap;
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u8 rfe_type;
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if (phl_is_mp_mode(rf->phl_com))
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rfe_type = rf->phl_com->dev_sw_cap.rfe_type;
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else
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rfe_type = rf->hal_com->dev_hw_cap.rfe_type;
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if (phy_hw[0].tx_num == 1 && phy_hw[0].tx_path_num == 2 &&
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phy_hw[0].rx_num == 1 && phy_hw[0].rx_path_num == 2) {
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if (rfe_type == 41) {
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RF_DBG(rf, DBG_RF_INIT, "%s: rfe_type: %d set to 1T1R\n", __func__, rfe_type);
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phy_hw[0].tx_path_num = 1;
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phy_hw[0].rx_path_num = 1;
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} else if (rfe_type == 43) {
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RF_DBG(rf, DBG_RF_INIT, "%s: rfe_type: %d set to 1T2R\n", __func__, rfe_type);
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phy_hw[0].tx_path_num = 2;
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phy_hw[0].rx_path_num = 2;
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}
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}
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}
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void halrf_txck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum dac_ck ck)
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{
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halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x0);
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if (!force)
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return;
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halrf_wreg(rf, 0x12a0 | (path <<13), 0x7000, ck);
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halrf_wreg(rf, 0x12a0 | (path <<13), BIT(15), 0x1);
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}
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void halrf_rxck_force_8852b(struct rf_info *rf, enum rf_path path, bool force, enum adc_ck ck)
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{
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halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x0);
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if (!force)
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return;
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halrf_wreg(rf, 0x12a0 | (path <<13), 0x70000, ck);
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halrf_wreg(rf, 0x12a0 | (path <<13), BIT(19), 0x1);
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}
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void halrf_arfc_si_reset_8852b(struct rf_info *rf, bool is_reset)
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{
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u8 val;
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/*reset adie HW/SW SI*/
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if (is_reset) {
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rtw_hal_mac_get_xsi((rf)->hal_com, 0x81, &val);
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val &= (~0xc0);
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rtw_hal_mac_set_xsi((rf)->hal_com, 0x81, val);
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rtw_hal_mac_get_xsi((rf)->hal_com, 0x80, &val);
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val &= (~0xc0);
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rtw_hal_mac_set_xsi((rf)->hal_com, 0x80, val);
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} else {
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rtw_hal_mac_get_xsi((rf)->hal_com, 0x81, &val);
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val |= 0xc0;
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rtw_hal_mac_set_xsi((rf)->hal_com, 0x81, val);
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rtw_hal_mac_get_xsi((rf)->hal_com, 0x80, &val);
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val |= 0xc0;
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rtw_hal_mac_set_xsi((rf)->hal_com, 0x80, val);
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}
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}
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void halrf_si_reset_8852b(struct rf_info *rf)
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{
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/*disable hwsi trigger*/
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halrf_wreg(rf, 0x1200, 0x70000000, 0x7);
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halrf_wreg(rf, 0x3200, 0x70000000, 0x7);
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halrf_delay_us(rf, 1);
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/*reset A die HW SI*/
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halrf_arfc_si_reset_8852b(rf, true);
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// reset D die HW SI*/
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halrf_wreg(rf, 0x12ac, BIT(0), 0x0);
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halrf_wreg(rf, 0x32ac, BIT(0), 0x0);
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/*release A die HW SI*/
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halrf_arfc_si_reset_8852b(rf, false);
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/*enable hwsi trigger*/
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halrf_wreg(rf, 0x1200, 0x70000000, 0x0);
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halrf_wreg(rf, 0x3200, 0x70000000, 0x0);
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/*release D die HW SI*/
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halrf_wreg(rf, 0x12ac, BIT(0), 0x1);
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halrf_wreg(rf, 0x32ac, BIT(0), 0x1);
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}
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#endif
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