/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef __HALRF_H__
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#define __HALRF_H__
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/*@--------------------------[Define] ---------------------------------------*/
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/*H2C cmd ID*/
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/*Class 8*/
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/*Class 9*/
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/*Class a*/
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#define FWCMD_H2C_BACKUP_RFK 0
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#define FWCMD_H2C_RELOAD_RFK 1
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#define FWCMD_H2C_GET_MCCCH 2
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#define FWCMD_H2C_DPK_OFFLOAD 3
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#define FWCMD_H2C_IQK_OFFLOAD 4
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#define FWCMD_H2C_PWR_TBL_OFFLOAD 5
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/*C2H classid*/
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enum halrf_c2h_classid {
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HALRF_C2H_RFK_LOG = 0x8,
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HALRF_MAX_C2HCMD
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};
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/*@--------------------------[Enum]------------------------------------------*/
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enum halrf_func_idx {
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RF00_PWR_TRK = 0,
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RF01_IQK = 1,
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RF02_LCK = 2,
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RF03_DPK = 3,
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RF04_TXGAPK = 4,
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RF05_DACK = 5,
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RF06_DPK_TRK = 6,
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RF07_2GBAND_SHIFT = 7,
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RF08_RXDCK = 8,
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RF09_RFK = 9,
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RF10_RF_INIT = 10,
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RF11_RF_POWER = 11,
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RF12_RXGAINK = 12,
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RF13_THER_TRIM = 13,
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RF14_PABIAS_TRIM = 14,
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RF15_TSSI_TRIM = 15,
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RF16_PSD = 16,
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RF17_TSSI_TRK = 17,
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RF18_XTAL_TRK = 18,
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RF19_TX_SHAPE = 19,
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RF20_OP5K_TRK = 20,
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RF21_OP5K = 21,
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RF22_TPE_CTRL = 22,
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RF23_RXDCK_TRK = 23,
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RF31_WATCHDOG = 31
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};
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enum halrf_rf_mode {
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RF_SHUT_DOWN = 0x0,
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RF_STANDBY = 0x1,
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RF_TX = 0x2,
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RF_RX = 0x3,
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RF_TXIQK = 0x4,
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RF_DPK = 0x5,
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RF_RXK1 = 0x6,
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RF_RXK2 = 0x7
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};
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enum halrf_rfe_src_sel {
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HALRF_PAPE_RFM = 0,
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HALRF_GNT_BT_INV = 1,
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HALRF_LNA0N = 2,
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HALRF_LNAON_RFM = 3,
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HALRF_TRSW_RFM = 4,
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HALRF_TRSW_RFM_B = 5,
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HALRF_GNT_BT = 6,
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HALRF_ZERO = 7,
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HALRF_ANTSEL_0 = 8,
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HALRF_ANTSEL_1 = 9,
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HALRF_ANTSEL_2 = 0xa,
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HALRF_ANTSEL_3 = 0xb,
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HALRF_ANTSEL_4 = 0xc,
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HALRF_ANTSEL_5 = 0xd,
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HALRF_ANTSEL_6 = 0xe,
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HALRF_ANTSEL_7 = 0xf
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};
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/*@=[HALRF supportability]=======================================*/
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enum halrf_ability {
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HAL_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
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HAL_RF_IQK = BIT(RF01_IQK),
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HAL_RF_LCK = BIT(RF02_LCK),
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HAL_RF_DPK = BIT(RF03_DPK),
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HAL_RF_TXGAPK = BIT(RF04_TXGAPK),
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HAL_RF_DACK = BIT(RF05_DACK),
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HAL_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
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HAL_2GBAND_SHIFT = BIT(RF07_2GBAND_SHIFT),
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HAL_RF_RXDCK = BIT(RF08_RXDCK),
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HAL_RF_RXGAINK = BIT(RF12_RXGAINK),
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HAL_RF_THER_TRIM = BIT(RF13_THER_TRIM),
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HAL_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
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HAL_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
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HAL_RF_TSSI_TRK = BIT(RF17_TSSI_TRK),
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HAL_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
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HAL_RF_TX_SHAPE = BIT(RF19_TX_SHAPE),
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HAL_RF_OP5K_TRACK = BIT(RF20_OP5K_TRK),
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HAL_RF_OP5K = BIT(RF21_OP5K),
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HAL_RF_TPE_CTRL = BIT(RF22_TPE_CTRL),
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HAL_RF_RXDCK_TRACK = BIT(RF23_RXDCK_TRK),
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HAL_RF_WATCHDOG = BIT(RF31_WATCHDOG),
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};
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/*@=[HALRF Debug Component]=====================================*/
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enum halrf_dbg_comp {
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DBG_RF_TX_PWR_TRACK = BIT(RF00_PWR_TRK),
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DBG_RF_IQK = BIT(RF01_IQK),
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DBG_RF_LCK = BIT(RF02_LCK),
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DBG_RF_DPK = BIT(RF03_DPK),
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DBG_RF_TXGAPK = BIT(RF04_TXGAPK),
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DBG_RF_DACK = BIT(RF05_DACK),
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DBG_RF_DPK_TRACK = BIT(RF06_DPK_TRK),
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DBG_RF_RXDCK = BIT(RF08_RXDCK),
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DBG_RF_RFK = BIT(RF09_RFK),
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DBG_RF_INIT = BIT(RF10_RF_INIT),
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DBG_RF_POWER = BIT(RF11_RF_POWER),
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DBG_RF_RXGAINK = BIT(RF12_RXGAINK),
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DBG_RF_THER_TRIM = BIT(RF13_THER_TRIM),
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DBG_RF_PABIAS_TRIM = BIT(RF14_PABIAS_TRIM),
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DBG_RF_TSSI_TRIM = BIT(RF15_TSSI_TRIM),
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DBG_RF_PSD = BIT(RF16_PSD),
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DBG_RF_XTAL_TRACK = BIT(RF18_XTAL_TRK),
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DBG_RF_OP5K_TRACK = BIT(RF20_OP5K_TRK),
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DBG_RF_OP5K = BIT(RF21_OP5K),
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DBG_RF_FW = BIT(28),
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DBG_RF_MP = BIT(29),
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DBG_RF_TMP = BIT(30),
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DBG_RF_CHK = BIT(31)
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};
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/*@--------------------------[Structure]-------------------------------------*/
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struct rfk_location {
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enum band_type cur_band;
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enum channel_width cur_bw;
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u8 cur_ch;
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};
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#define OP5K_RESET_CNT_DATA 16
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#define OP5K_RESET_CNT_ZERO_IDX 2
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#define OP5K_THERMAL_NUM 2
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#define OP5K_AVG_THERMAL_NUM 2
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#define OP5K_THER_THRESHOLD 8
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struct halrf_op5k_info {
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u32 rst_cnt[MAX_RF_PATH][OP5K_RESET_CNT_DATA];
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u32 rst_cnt_zero[MAX_RF_PATH][OP5K_RESET_CNT_ZERO_IDX];
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u32 rst_cnt_final[MAX_RF_PATH];
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u32 op5k_backup[MAX_RF_PATH];
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u8 thermal_op5k[MAX_RF_PATH];
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u8 thermal_op5k_avg[MAX_RF_PATH][OP5K_THERMAL_NUM];
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u8 thermal_op5k_avg_index;
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bool op5k_progress;
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u8 record_bw;
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};
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#if 1 /* all rf operation usage (header) */
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/* clang-format on */
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#define RF_PATH_MAX_NUM (8)
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#define RF_TASK_RECORD_MAX_TIMES (16)
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#define RF_BACKUP_MAC_REG_MAX_NUM (16)
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#define RF_BACKUP_BB_REG_MAX_NUM (16)
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#define RF_BACKUP_RF_REG_MAX_NUM (16)
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#define RF_BACKUP_KIP_REG_MAX_NUM (16)
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struct halrf_iqk_ops {
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u8 (*iqk_kpath)(struct rf_info *rf, enum phl_phy_idx phy_idx);
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bool (*iqk_mcc_page_sel)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
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void (*iqk_get_ch_info)(struct rf_info *rf, enum phl_phy_idx phy, u8 path);
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void (*iqk_preset)(struct rf_info *rf, u8 path);
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void (*iqk_macbb_setting)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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void (*iqk_start_iqk)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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void (*iqk_restore)(struct rf_info *rf, u8 path);
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void (*iqk_afebb_restore)(struct rf_info *rf, enum phl_phy_idx phy_idx, u8 path);
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};
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struct rfk_iqk_info {
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struct halrf_iqk_ops *rf_iqk_ops;
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u8 rf_max_path_num;
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u32 rf_iqk_version;
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u8 rf_iqk_ch_num;
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u8 rf_iqk_path_num;
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const u32 *backup_mac_reg;
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u32 backup_mac_reg_num;
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const u32 *backup_bb_reg;
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u32 backup_bb_reg_num;
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const u32 *backup_rf_reg;
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u32 backup_rf_reg_num;
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};
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/* clang-format off */
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#endif /* all rf operation usage (header) */
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struct halrf_rx_dck_info {
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bool is_afe;
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bool is_rxdck_track_en;
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struct rfk_location loc[KPATH]; /*max RF path*/
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u32 rxdck_time;
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bool is_auto_res;
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u8 ther_rxdck[KPATH];
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u8 rek_cnt[KPATH];
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};
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struct halrf_mcc_info {
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u8 ch[2];
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u8 band[2];
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u8 table_idx;
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bool is_init;
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};
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struct halrf_dbcc_info {
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u8 ch[2][2]; /*idx : path*/
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u8 band[2][2];
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u8 table_idx;
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bool prek_is_dbcc;
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bool is_free[2];
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};
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struct halrf_rfk_ops {
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void (*halrf_ops_rx_dck)(struct rf_info *rf, enum phl_phy_idx phy, bool is_afe);
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void (*halrf_ops_do_txgapk)(struct rf_info *rf, enum phl_phy_idx phy);
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void (*halrf_ops_tssi_disable)(struct rf_info *rf, enum phl_phy_idx phy);
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void (*halrf_ops_do_tssi)(struct rf_info *rf, enum phl_phy_idx phy, bool hwtx_en);
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void (*halrf_ops_dpk)(struct rf_info *rf, enum phl_phy_idx phy, bool force);
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void (*halrf_ops_dack)(struct rf_info *rf, bool force);
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void (*halrf_ops_lck)(struct rf_info *rf);
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void (*halrf_ops_lck_tracking)(struct rf_info *rf);
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void (*halrf_ops_lo_test)(struct rf_info *rf, bool is_on, enum rf_path path);
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void (*halrf_config_radio_to_fw)(struct rf_info *rf);
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void (*halrf_ops_txgapk_w_table_default)(struct rf_info *rf, enum phl_phy_idx phy);
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void (*halrf_ops_txgapk_enable)(struct rf_info *rf, enum phl_phy_idx phy);
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void (*halrf_ops_txgapk_init)(struct rf_info *rf);
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void (*halrf_ops_adie_pow_ctrl)(struct rf_info *rf, bool rf_off, bool others_off);
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void (*halrf_ops_afe_pow_ctrl)(struct rf_info *rf, bool adda_off, bool pll_off);
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void (*halrf_ops_set_gpio_by_ch)(struct rf_info *rf, enum phl_phy_idx phy, enum band_type band);
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};
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struct halrf_rt_rpt {
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u32 ch_info[10][2][2]; //last10 /cv
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u8 tssi_code[10][2]; //tssi/path
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u32 drv_lck_fail_count;
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u32 fw_lck_fail_count;
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};
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struct halrf_rfk_dz_rpt {
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u32 iqk_dz_code;
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u32 dpk_dz_code;
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u32 dack_s0_dz_code;
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u32 dack_s1_dz_code;
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u32 rxdck_dz_code;
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u32 txgapk_dz_code;
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u32 tssi_dz_code;
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};
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//===========
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struct rf_info {
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struct rtw_phl_com_t *phl_com;
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struct rtw_hal_com_t *hal_com;
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/*[Common Info]*/
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u32 ic_type;
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u8 num_rf_path;
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u16 sub_did;
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bool use_sub_did;
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/*[System Info]*/
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bool rf_init_ready;
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u32 rf_sys_up_time;
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bool rf_watchdog_en;
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bool rf_ic_api_en;
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/*[DM Info]*/
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u32 support_ability;
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u32 hw_rf_ability;
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u32 manual_support_ability;
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/*[FW Info]*/
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u32 fw_dbg_component;
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/*[Drv Dbg Info]*/
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u32 dbg_component;
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u8 cmn_dbg_msg_period;
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u8 cmn_dbg_msg_cnt;
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/*[BTC / RFK Info ]*/
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bool rfk_is_processing;
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bool is_bt_iqk_timeout;
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bool is_chl_rfk;
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u32 rfk_total_time;
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/*[initial]*/
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u8 pre_rxbb_bw[KPATH];
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/*[TSSI Info]*/
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bool is_tssi_mode[MAX_RF_PATH]; /*S0/S1*/
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u8 tssi_slope_type[MAX_RF_PATH];
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/*[Thermal]*/
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bool is_thermal_trigger;
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u8 cur_ther_s0;
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u8 cur_ther_s1;
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/*LCK*/
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u8 lck_ther_s0;
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u8 lck_ther_s1;
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u32 lck_times;
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/*[Do Coex]*/
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bool is_coex;
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/*[watchdog]*/
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bool is_watchdog_stop;
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/*[thermal rek indictor]*/
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bool rfk_do_thr_rek;
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/*reg check*/
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u32 rfk_reg[KIP_REG];
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u32 rfc_reg[2][10];
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u32 rfk_check_fail_count;
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/*fast channel switch*/
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u8 ther_init;
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u32 fcs_rfk_ok_map;
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u8 pre_chl_idx;
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u8 pre_ther_idx;
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/* [Check NCTL Done status Read Times] */
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u32 nctl_ck_times[2]; /* 0xbff8 0x80fc*/
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u32 fw_ofld_enable;
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u32 fw_ofld_start;
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/*IO/FW offload count*/
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u32 w_count;
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u32 r_count;
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u32 fw_w_count;
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u32 fw_r_count;
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u32 sw_trigger_count;
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u32 pre_fw_w_count;
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u32 fw_delay_us_count;
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u32 init_rf_reg_time;
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u32 set_ch_bw_time;
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_os_mutex rf_lock;
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u32 chlk_map;
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u32 kip_table[2][4];
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/*@=== [HALRF Structure] ============================================*/
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struct halrf_pwr_track_info pwr_track;
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struct halrf_tssi_info tssi;
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struct halrf_xtal_info xtal_track;
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struct halrf_iqk_info iqk;
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struct halrf_dpk_info dpk;
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struct halrf_rx_dck_info rx_dck;
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struct halrf_dack_info dack;
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struct halrf_gapk_info gapk;
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struct halrf_pwr_info pwr_info;
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struct halrf_fw_scan_pwr_info pwr_fw_info;
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struct halrf_radio_info radio_info;
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struct halrf_fem_info fem;
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struct rf_dbg_cmd_info rf_dbg_cmd_i;
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struct halrf_kfree_info kfree_info;
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struct halrf_psd_data psd;
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struct rfk_location iqk_loc[2]; /*S0/S1*/
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struct rfk_location dpk_loc[2]; /*S0/S1*/
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struct rfk_location gapk_loc[2]; /*S0/S1*/
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struct rfk_iqk_info *rfk_iqk_info;
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struct halrf_op5k_info op5k_info;
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struct halrf_mcc_info mcc_info;
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struct halrf_dbcc_info dbcc_info;
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//
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struct halrf_rfk_ops *rf_rfk_ops;
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struct halrf_rt_rpt rf_rt_rpt;
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struct halrf_rfk_dz_rpt rfk_dz_rpt;
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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void halrf_si_reset(struct rf_info *rf);
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#endif
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