/******************************************************************************
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*
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* Copyright(c) 2019 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*****************************************************************************/
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#ifndef _HALBB_PLCP_TX_L_ENDIAN_H_
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#define _HALBB_PLCP_TX_L_ENDIAN_H_
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/*@--------------------------[Define] ---------------------------------------*/
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#define DL_STA_LIST_MAX_NUM 8
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/*@--------------------------[Enum]------------------------------------------*/
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/*@--------------------------[Structure]-------------------------------------*/
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#if 0
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struct cr_address_t {
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u8 address_0;
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u8 address_1;
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u8 address_2;
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u8 address_3;
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u8 bitmask_0;
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u8 bitmask_1;
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u8 bitmask_2;
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u8 bitmask_3;
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};
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struct ru_rate_entry {
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u8 dcm: 1;
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u8 ss: 3;
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u8 mcs: 4;
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};
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struct rura_report {
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u8 rate_table_col_idx: 6;
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u8 partial_allocation_flag: 1;
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u8 rate_change_flag: 1;
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};
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struct dl_ru_output_sta_entry {
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// DW0
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u8 dropping_flag: 1; //0
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u8 txbf: 1;
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u8 coding: 1;
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u8 nsts: 3;
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u8 ps160: 1;
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u8 rsvd0: 1;
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u8 mac_id;
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u8 ru_position;
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u8 vip_flag: 1; //dont care
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u8 pwr_boost_factor: 5; //dont care
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u8 rsvd1: 2;
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// DW1
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u8 tx_length_0;
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u8 tx_length_1;
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u8 tx_length_2;
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u8 tx_length_3;
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// DW2
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struct ru_rate_entry ru_rate;
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struct rura_report ru_ra_report;
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u8 aid12_0;
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u8 aid12_1: 3;
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u8 rsvd2: 5;
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};
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struct dl_rua_output {
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// DW0
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u8 ru2su_flag: 1;
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u8 ppdu_bw: 2; //set
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u8 group_tx_pwr_0: 5;
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u8 group_tx_pwr_1: 4;
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u8 stbc: 1;
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u8 gi_ltf: 3;
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u8 doppler: 1;
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u8 n_ltf_and_ma: 3;
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u8 sta_list_num: 4; //set
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u8 grp_mode: 1;
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u8 rsvd0: 6;
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u8 fixed_mode: 1; //set 1
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// DW1
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u8 group_id;
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u8 ch20_with_data_0;
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u8 ch20_with_data_1;
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u8 pri_txsb: 5;
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u8 ru_grp_ntx: 3;
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// DW2 (new added)
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u8 ul_dl: 2;
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u8 ppdu_type_comp_mode: 2;
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u8 usig_spat_reuse: 4;
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u8 usig_ltf_symb: 3;
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u8 usig_nss: 4;
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u8 usig_bf: 1;
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u8 usig_spat_gi_ltf: 2;
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u8 usig_disregard_ndp: 2;
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u8 usig_ldpc_extra_symb_seg: 1;
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u8 usig_prefec: 2;
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u8 usig_pe_disambiguity: 1;
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u8 usig_disregard: 4;
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u8 rsvd1: 4;
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// DW3
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struct dl_ru_output_sta_entry dl_output_sta_list[8];
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};
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//sig output
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struct sigb_compute_output {
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// DW0
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u8 sta_0_idx: 3;
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u8 sta_1_idx: 3;
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u8 sta_2_idx_0: 2;
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u8 sta_2_idx_1: 1;
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u8 sta_3_idx: 3;
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u8 sta_4_idx: 3;
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u8 sta_5_idx_0: 1;
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u8 sta_5_idx_1: 2;
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u8 sta_6_idx: 3;
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u8 sta_7_idx: 3;
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u8 rsvd0;
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// DW1
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u8 hw_sigb_content_channelone_len;
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u8 hw_sigb_content_channeltwo_len;
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u8 hw_sigb_symbolnum: 6;
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u8 hw_sigb_content_channeltwo_offset_0: 2; //have to +1
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u8 hw_sigb_content_channeltwo_offset_1: 3; //have to +1
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u8 ru2su_flag: 1;
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u8 sigb_dcm: 1;
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u8 sigb_mcs: 3;
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// DW2 (new added)
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u8 HW_EHTSIG_1st80_content_channelone_len_0;
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u8 HW_EHTSIG_1st80_content_channelone_len_1: 2;
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u8 HW_EHTSIG_1st80_content_channeltwo_len_0: 6;
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u8 HW_EHTSIG_1st80_content_channeltwo_len_1: 4;
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u8 rsvd1: 4;
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u8 rsvd2;
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// DW3 (new added)
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u8 HW_EHTSIG_2nd80_content_channelone_len_0;
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u8 HW_EHTSIG_2nd80_content_channelone_len_1: 2;
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u8 HW_EHTSIG_2nd80_content_channeltwo_len_0: 6;
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u8 HW_EHTSIG_2nd80_content_channeltwo_len_1: 4;
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u8 rsvd3: 4;
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u8 rsvd4;
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// DW4 (new added)
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u8 HW_EHTSIG_3rd80_content_channelone_len_0;
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u8 HW_EHTSIG_3rd80_content_channelone_len_1: 2;
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u8 HW_EHTSIG_3rd80_content_channeltwo_len_0: 6;
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u8 HW_EHTSIG_3rd80_content_channeltwo_len_1: 4;
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u8 rsvd5: 4;
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u8 rsvd6;
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// DW5 (new added)
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u8 HW_EHTSIG_4th80_content_channelone_len_0;
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u8 HW_EHTSIG_4th80_content_channelone_len_1: 2;
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u8 HW_EHTSIG_4th80_content_channeltwo_len_0: 6;
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u8 HW_EHTSIG_4th80_content_channeltwo_len_1: 4;
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u8 rsvd7: 4;
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u8 rsvd8;
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};
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struct bb_h2c_sig_info {
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u8 force_sigb_rate;
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u8 force_sigb_mcs;
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u8 force_sigb_dcm;
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u8 rsvd;
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struct dl_rua_output dl_rua_out;
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struct sigb_compute_output sigb_output;
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struct cr_address_t n_sym_hesigb_ehtsig[156];
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};
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#else
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struct halbb_ehtsig_rpt_info {
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u8 ehtsig_sym_num;
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u8 ru2su_flag;
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u8 c2h_done;
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u8 rsvd1;
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};
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struct cr_address_t {
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u8 address_0;
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u8 address_1;
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u8 address_2;
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u8 address_3;
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};
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// EHT SIG & SIGB
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struct ehtsig_sigb_usr_info {
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u8 coding;
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u8 nsts;
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u8 ru_position;
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u8 dcm;
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u8 mcs;
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u8 ps160;
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u8 rsvd0;
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u8 rsvd1;
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};
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struct ehtsig_sigb_info {
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u8 ppdu_bw;
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u8 sta_list_num;
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u8 ch20_with_data_0;
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u8 ch20_with_data_1;
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u8 pri_txsb;
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u8 ul_dl;// 2 bit
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u8 ppdu_type_comp_mode;// 2 bit
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u8 usig_spat_reuse;// 4 bit
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u8 usig_ltf_symb;// 3 bit
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u8 usig_nss;// 4 bit
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u8 usig_bf;// 1 bit
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u8 usig_spat_gi_ltf;// 2 bit
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u8 usig_disregard_ndp;// 2 bit
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u8 usig_ldpc_extra_symb_seg;// 1 bit
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u8 usig_prefec;// 2 bit
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u8 usig_pe_disambiguity;// 1 bit
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u8 usig_disregard;// 4 bit
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u8 rsvd0;
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u8 rsvd1;
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u8 rsvd2;
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struct ehtsig_sigb_usr_info usr_info[DL_STA_LIST_MAX_NUM];
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};
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struct bb_h2c_ehtsig_sigb {
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u8 ehtsig_sigb; // (True): EHT-SIG / (False): SIG-B
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u8 ehtsig_sigb_mcs;
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u8 phy_idx;
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u8 rsvd3;
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struct ehtsig_sigb_info ehtsig_sigb_i;
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struct cr_address_t ehtsig_sigb_cr[80];
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};
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/*@--------------------------[Prptotype]-------------------------------------*/
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#endif
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#endif
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