/******************************************************************************
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*
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* Copyright(c) 2007 - 2020 Realtek Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called LICENSE.
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*
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* Contact Information:
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* wlanfae <wlanfae@realtek.com>
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* Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
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* Hsinchu 300, Taiwan.
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*
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* Larry Finger <Larry.Finger@lwfinger.net>
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*
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*****************************************************************************/
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#ifndef _HALBB_OUTSRC_DEF_H_
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#define _HALBB_OUTSRC_DEF_H_
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/* ============================================================
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define
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============================================================
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*/
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#define N_USER 4
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/* ============================================================
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Enumeration
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============================================================
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*/
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#include "halbb_bb_wrapper_outsrc.h"
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enum mlo0_mode {
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MLO0_0_PATH = 0x0,
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MLO0_1_PATH = 0x1,
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MLO0_2_PATH = 0x2,
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MLO0_3_PATH = 0x3,
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};
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enum mlo1_mode {
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MLO1_0_PATH = 0x0,
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MLO1_1_PATH = 0x10,
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MLO1_2_PATH = 0x20,
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MLO1_3_PATH = 0x30,
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};
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enum bb_mlo_mode_info {
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MLO_0_PLUS_2 = (MLO1_0_PATH | MLO0_2_PATH),
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MLO_1_PLUS_1 = (MLO1_1_PATH | MLO0_1_PATH),
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MLO_2_PLUS_0 = (MLO1_2_PATH | MLO0_0_PATH),
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MLO_2_PLUS_2 = (MLO1_2_PATH | MLO0_2_PATH)
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};
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enum halbb_dbcc_mode_type {
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BB_DBCC_NOT_SUPPORT = 0,
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BB_DBCC_MLO_0_PLUS_2 = (MLO1_0_PATH | MLO0_2_PATH),
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BB_DBCC_MLO_1_PLUS_1 = (MLO1_1_PATH | MLO0_1_PATH),
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BB_DBCC_MLO_2_PLUS_0 = (MLO1_2_PATH | MLO0_0_PATH),
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BB_DBCC_MLO_2_PLUS_2 = (MLO1_2_PATH | MLO0_2_PATH),
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BB_DBCC_SINGLE_MAC = 0xff
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};
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enum plcp_sts {
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PLCP_SUCCESS = 0,
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LENGTH_EXCEED,
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CCK_INVALID,
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OFDM_INVALID,
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HT_INVALID,
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VHT_INVALID,
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HE_INVALID,
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EHT_INVALID,
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SPEC_INVALID
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};
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enum plcp_dbw {
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DBW20 = 0,
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DBW40,
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DBW80,
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DBW160,
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DBW320
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};
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enum ru_sizes_list {
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RU26 = 0,
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RU52,
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RU106,
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RU242,
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RU484,
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RU996,
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RU996X2,
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HESIGB,
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RU996X4,
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RU52_26,
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RU106_26,
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RU484_242,
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RU996_484,
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RU996_484_242,
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RU996X2_484,
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RU996X3,
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RU996X3_484,
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RU_SIZE_NUM
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};
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enum packet_format_t{
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B_MODE_FMT = 0,
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LEGACY_FMT,
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HT_MF_FMT,
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HT_GF_FMT,
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VHT_FMT,
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HE_SU_FMT,
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HE_ER_SU_FMT,
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HE_MU_FMT,
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HE_TB_FMT,
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EHT_MU_SU_FMT,
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EHT_MU_MU_FMT, // MU-MIMO
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EHT_MU_RU_FMT, // DL MU-OFDMA
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EHT_MU_ERSU_FMT,
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EHT_TB_FMT
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};
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/* ============================================================
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structure
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============================================================
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*/
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#if 0
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struct cr_address_t {
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u32 address;
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u32 bitmask;
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};
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struct ru_rate_entry {
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u8 dcm: 1;
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u8 ss: 3;
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u8 mcs: 4;
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};
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struct rura_report {
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u8 rate_table_col_idx: 6;
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u8 partial_allocation_flag: 1;
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u8 rate_change_flag: 1;
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};
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struct dl_ru_output_sta_entry {
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// DW0
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u32 dropping_flag: 1; //0
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u32 txbf: 1;
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u32 coding: 1;
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u32 nsts: 3;
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u32 ps160: 1;
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u32 rsvd0: 1;
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u32 mac_id: 8;
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u32 ru_position: 8;
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u32 vip_flag: 1; //dont care
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u32 pwr_boost_factor: 5; //dont care
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u32 rsvd1: 2;
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// DW1
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u32 tx_length;
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// DW2
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struct ru_rate_entry ru_rate;
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struct rura_report ru_ra_report;
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u32 aid12: 11;
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u32 rsvd2: 5;
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};
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struct dl_rua_output {
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// DW0
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u32 ru2su_flag: 1;
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u32 ppdu_bw: 2; //set
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u32 group_tx_pwr: 9;
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u32 stbc: 1;
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u32 gi_ltf: 3;
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u32 doppler: 1;
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u32 n_ltf_and_ma: 3;
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u32 sta_list_num: 4; //set
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u32 grp_mode: 1;
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u32 rsvd0: 6;
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u32 fixed_mode: 1; //set 1
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// DW1
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u32 group_id: 8;
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u32 ch20_with_data: 16;
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u32 pri_txsb: 5;
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u32 ru_grp_ntx: 3;
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// DW2 (new added)
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u32 ul_dl: 2;
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u32 ppdu_type_comp_mode: 2;
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u32 usig_spat_reuse: 4;
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u32 usig_spat_gi_ltf: 2;
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u32 usig_ltf_symb: 3;
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u32 usig_nss: 4;
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u32 usig_bf: 1;
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u32 usig_disregard_ndp: 2;
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u32 usig_ldpc_extra_symb_seg: 1;
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u32 usig_prefec: 2;
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u32 usig_pe_disambiguity: 1;
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u32 usig_disregard: 4;
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u32 rsvd1: 4;
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// DW3
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struct dl_ru_output_sta_entry dl_output_sta_list[DL_STA_LIST_MAX_NUM];
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};
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//sig output
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struct sigb_compute_output {
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// DW0
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u32 sta_0_idx: 3;
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u32 sta_1_idx: 3;
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u32 sta_2_idx: 3;
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u32 sta_3_idx: 3;
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u32 sta_4_idx: 3;
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u32 sta_5_idx: 3;
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u32 sta_6_idx: 3;
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u32 sta_7_idx: 3;
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u32 rsvd: 8;
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// DW1
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u32 hw_sigb_content_channelone_len: 8;
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u32 hw_sigb_content_channeltwo_len: 8;
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u32 hw_sigb_symbolnum: 6;
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u32 hw_sigb_content_channeltwo_offset: 5; //have to +1
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u32 ru2su_flag: 1;
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u32 sigb_dcm: 1;
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u32 sigb_mcs: 3;
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// DW2 (new added)
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u32 HW_EHTSIG_1st80_content_channelone_len: 10;
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u32 HW_EHTSIG_1st80_content_channeltwo_len: 10;
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u32 rsvd1: 12;
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// DW3 (new added)
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u32 HW_EHTSIG_2nd80_content_channelone_len: 10;
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u32 HW_EHTSIG_2nd80_content_channeltwo_len: 10;
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u32 rsvd2: 12;
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// DW4 (new added)
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u32 HW_EHTSIG_3rd80_content_channelone_len: 10;
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u32 HW_EHTSIG_3rd80_content_channeltwo_len: 10;
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u32 rsvd3: 12;
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// DW5 (new added)
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u32 HW_EHTSIG_4th80_content_channelone_len: 10;
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u32 HW_EHTSIG_4th80_content_channeltwo_len: 10;
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u32 rsvd4: 12;
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};
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struct bb_h2c_sig_info {
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u8 force_sigb_rate;
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u8 force_sigb_mcs;
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u8 force_sigb_dcm;
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u8 rsvd;
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struct dl_rua_output dl_rua_out;
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struct sigb_compute_output sigb_output;
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struct cr_address_t n_sym_sigb_ch1[16];
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struct cr_address_t n_sym_sigb_ch2[16];
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};
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#endif
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//========== [Outer-Input] ==========//
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enum path_div_en_t {
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BB_PATH_DIV_DISABLE = 0,
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BB_PATH_DIV_ENABLE = 1/*for auto path selection*/
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};
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struct bb_tx_path_en_info {
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bool max_tx_path_en; /*[Dbg mode] if = 1, set path with MAX_num in all different sts. Path_div will be disabled*/
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u8 max_tx_ss; /*TXss: phl_com->phy_cap[0].txss*/
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enum path_div_en_t path_div_en; /*if = 1, logic map control by HALBB path_div algorithm*/
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enum bb_path bb_path_1sts; /*if (bb_path_1sts == BB_PATH_BCD), means TX 1ss by path B & C & D, simultaneously*/
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enum bb_path bb_path_2sts;
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enum bb_path bb_path_3sts;
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enum bb_path bb_path_4sts;
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};
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struct bb_rx_path_en_info {
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enum bb_path rx_path_en; /*(rx_path_en == BB_PATH_ABCD), means RX by path A & B & C & D, simultaneously*/
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u8 rx_ss; /*RXss: phl_com->phy_cap[0].rxss*/
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};
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struct usr_plcp_gen_in {
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u8 mcs; //6-bit
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u16 mpdu_len; //14-bit
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u16 n_mpdu; //9-bit
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u8 fec; //1-bit
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u8 dcm; //1-bit
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u16 aid; //12-bit
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u8 scrambler_seed; //8-bit: rand (1~255)
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u8 random_init_seed; //8-bit: rand (1~255)
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u32 apep; //22-bit
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u8 ru_alloc; //8-bit
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u8 nss; //4-bit
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u8 txbf; //1-bit
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u8 pwr_boost_db; //5-bit
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u8 ru_size; //8-bit
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u8 ru_idx; //8-bit
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};
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struct halbb_plcp_info {
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u8 source_gen_mode; //2-bit
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u8 locked_clk; //1-bit
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u8 dyn_bw; //1-bit
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u8 ndp_en; //1-bit
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u8 long_preamble_en; //1-bit: bmode
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u8 stbc; //1-bit
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u8 gi; //2-bit: 0:0.4,1:0.8,2:1.6,3:3.2
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u16 tb_l_len; //12-bit
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u8 tb_ru_tot_sts_max; //3-bit
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u8 vht_txop_not_allowed; //1-bit
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u8 tb_disam; //1-bit
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u8 doppler; //2-bit
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u8 he_ltf_type; //2-bit: 0:1x,1:2x,2:4x
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u16 ht_l_len; //12-bit
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u8 preamble_puncture; //1-bit
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u8 he_mcs_sigb; //3-bit: 0~5
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u8 he_dcm_sigb; //1-bit
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u8 he_sigb_compress_en; //1-bit
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u16 max_tx_time_0p4us; //14-bit
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u8 ul_flag; //1-bit
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u8 tb_ldpc_extra; //1-bit
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u8 bss_color; //6-bit
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u8 sr; //4-bit
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u8 beamchange_en; //1-bit
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u8 he_er_u106ru_en; //1-bit
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u8 ul_srp1; //4-bit
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u8 ul_srp2; //4-bit
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u8 ul_srp3; //4-bit
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u8 ul_srp4; //4-bit
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u8 mode; //2-bit
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u8 group_id; //6-bit
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u8 ppdu_type; //4-bit: 0: bmode,1:Legacy,2:HT_MF,3:HT_GF,4:VHT,5:HE_SU,6:HE_ER_SU,7:HE_MU,8:HE_TB,9:EHT_SU,10:EHT_MU,11:EHT_RU,12:EHT_ERSU,13:EHT_TB
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u8 txop; //7-bit
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u8 tb_strt_sts; //3-bit
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u8 tb_pre_fec_padding_factor; //2-bit
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u8 txsc; //4-bit
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u8 tb_mumimo_mode_en; //1-bit
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u8 dbw; //3-bit: 0:BW20, 1:BW40, 2:BW80, 3:BW160/BW80+80, 4:BW320
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u8 nominal_t_pe; //2-bit: def = 2
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u8 ness; //2-bit: def = 0
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u8 cbw; //3-bit
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u8 n_user; //8-bit
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u16 tb_rsvd; //9-bit
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u8 punc_pattern; //8-bit
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u8 eht_mcs_sig; //8-bit
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u8 txsb; //8-bit
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struct usr_plcp_gen_in usr[N_USER];
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};
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/* ============================================================
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Function Prototype
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============================================================
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*/
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struct bb_info;
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enum plcp_sts halbb_plcp_gen(struct bb_info *bb, struct halbb_plcp_info *in,
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struct usr_plcp_gen_in *user, enum phl_phy_idx phy_idx);
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#endif
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